Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Xilinx doesn't detect setup/hold violations on synchronous reset
Hi all, I am facing some problems with Xilinx ISE 8.2 not taking into account synchronous reset setup/hold violations on FFs. My code looks like this: Inst_my_dcm_a: my_dcm PORT MAP( CLKIN_IN =>...
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16 years ago
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Atmel release Metal Programmable Cell Fabric uC ARM9
have done mask-metal flows for many years, this seems a simple/logical coupling with their exisiting CPU+Peripheral devices. NRE costs start at $150K, which I think is not bad compared with the other...
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16 years ago
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How to copy hex data from Quartus vwf file to text?
I'm just getting started with Quartus II v7.0. I have a test vwf file for some existing vhdl. I'd like to copy the 128 bit hex values from the vwf to a text file for my documentation. I can't seem to...
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16 years ago
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ModelSim version upgrade problem from 6.1c to 6.2c
Hi, When my ModelSim version is upgraded from 6.1c to 6.2c, a new problem happens: When opening file, either created by 6.1c version or 6.2c version, the following error information would appear: #...
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16 years ago
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Does FPGA need CPU for processing a packet/frame
I would like to know if an FPGA needs CPU for processing a packet/ frame that it receives. For example an FPGA is capable of processing a frame based on its destination Address (similar to layer 2...
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16 years ago
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SelectIO banking rules
Hi, Can I drive a LCVMOS25 (input) and a LVTTL (input/output) in the same bank even if there is VCCIO problems ? Thanks!
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16 years ago
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Error in NGDBuild
Hello everybody, I was trying NGDbuild for a DDR memory controller implementation. I am getting the following error: ERROR:NgdBuild:924 - bidirect pad net 'cntrl0_ddr1_dq(0)' is driving non-buffer...
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16 years ago
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Cyclone FPGAs in Switzerland
EHLO (o; I tried several weeks ago to contact EBV Switzerland where to get EP1C and EP2C devices in smaller quantities than their 60/90 package size...but never got any feedback... Also their website...
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16 years ago
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Timing not met but working on board
Hi all, I developed a design in which i need a master clock of 90Mhz, so during synthesis max. freq obtained is 56Mhz and timing is met for global clock of 50Mhz, but timing are not met for 90Mhz. but...
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16 years ago
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Filtering the FPGA reset signal
Hello, On my board, the FPGA receives its reset_n signal from a voltage supervisor IC (such as MAX635x or LM370x). Is there a point to further filter (digitally) this signal upon entry into the FPGA ?...
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16 years ago
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UART Receiver Parity Check
Hello, I'm trying to learn VHDL and here I'm adding a parity bit to Ben Cohen's UART Receiver. RxReg(9) is incoming parity bit from transmitter side. A 0 output at Parity_err means no parity error...
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16 years ago
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AccelDSP Systemgenerator ML403
Hello, i need help with my ml403. I would like to get a my ML403 Board from Xilinx run with Systemgeneratior. That i can make a Ethernet connection between Matlab and the Board. Where do i find...
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16 years ago
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Signal Assignment bugs in Quartus-II ... AGAIN!
I've repeatedly reported this blatant and repeatedly acknowledged bug in Quartus-II's schematic editor, yet it appears it's still there in all its splendor in v7.1. When I assign a bus named the...
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16 years ago
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external clock frequency doubles
Hi People, I am attempting to interface the Xilinx Virtex - II Pro FPGA with a quad channel codec. I am using XC2VP30-FF896 FPGA on the Xilinx University Program Development Board.I had applied a...
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16 years ago
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EDK 8.1i to EDK 9.1i UCF file errors
Hello, In our *working* EDK 8.1i project, we locked a DCM in the following manner in the UCF file (located in /data/system.ucf): INST dcm_sys/dcm_sys/DCM_INST LOC = DCM_X0Y0; INST...
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16 years ago
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