Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Ddr sdram feedback pin
Hi everyone, I want to design a model with my Smt338. This is a Sundance board with a Virtex IIPro30 ff896-6 and a Micron MT46V16M16 as DDR memory. First of all I need to implement the hardware...
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16 years ago
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How can i command bit Inputs in an FPGA board?
How can i command bit Inputs in an FPGA board?
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16 years ago
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LVDS termination scheme to nonstandard ribbon cable
Hi I am doing a Spartan3 to Spartan 3 interconnect trough a ribbon (flat) cable with a characteristic impedance of 173R balanced (103R unbalanced). I have tried xilinx webcase to answer on the...
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16 years ago
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6502 and CPU licences in general
I've found a 6502 core at , which is based on a version from which looks like it turned into an advertising site, but I've found the original page at Under "Legal Stuff" it says "Currently, there are...
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16 years ago
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Error while generating Libraries and BSPs.
Hi, I am at my initial stage of design with a Microblaze which is connected to two peripherals through FSLs. The connection is like Microblaze -> peripheral_1 -> peripheral_2 -> back to Microblaze....
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16 years ago
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SATA OOB detection with Virtex5
Hi to all i would to use SATA OOB detection with Virtex5 GTPs. Iam using the ML505 development board with the two SATA connectors, connected with the crossovercable. Now to the problem: if i sends an...
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16 years ago
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fit_timer: trouble connecting interrupt
In my application, I was trying to switch from using an opb_timer to a fit_timer to save on resources, but seem to be having some trouble correctly connecting the interrupt. I wire the interrupt from...
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16 years ago
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Custom Memory Initialization
Hi, I need your help for some problem using the Xilinx EDK in simulation and profiling. The system I have designed is composed by a Microblaze and an OPB customized peripheral, built by the peripheral...
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16 years ago
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Altera Cyclone II - used in 100USD Laptop
pretty interesting - so funny that makes you wanna a child again ;) ok, the price is not 100 but 150, guess the manufacturer did not meed the 100 USD goal Antti
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16 years ago
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problem while reading from DDR 2 memory
Hi to all I am currently working on DDR2 controller for Burst Lenth 8. My own code is giving good results when i verified with memory model from MICRON. Now my problem is memory on the board is not...
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16 years ago
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clarification: clock doubling in Spartan 3
If we design an S3-based system using an internal clock doubler, the design software wants to know our input frequency. In our case, we want to double the incoming 20 MHz clock to 40 MHz for internal...
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16 years ago
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Binary to BCD
Hello all. I'm very new to VHDL and stuck with a simple task. This code should convert binary number to BCD number using shift and add= 3 = algoritam After this code executes I always get "0000" in...
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16 years ago
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Project Navigator / Verilog / +define
I'm having a problem with Xilinx Navigator "discovering" a Verilog design hierarchy. I've inherited some IP that requires that a Verilog `define be set to specify the modules to include into the...
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16 years ago
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Xilinx ML405 / VxWorks 6.3 Bootloader
Hi, Anyone had experience of creating a VxWorks Bootloader that will run on a Xilinx ML40x Evaluation Platform? I have created a bootloader and have loaded it into flash but it will not run from...
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16 years ago
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DDR SDRAM in custom board
Hi everyone. I have a virtex II pro in a custom board (sundance board) and a Micron MT46V16M16. I use edk to create a design with PowerPC and the DDR. I select custom board and I finally get my...
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16 years ago
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