Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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low speed communication
Hi everybody, I have two Virtex4 FX12 Minimodules and I'd like to make them communicate eachother. These modules don't have any special transciver (RocketIO, ...) and are equipped with one PPC. The...
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16 years ago
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IOSTANDARD user constrain
Hi, Is there a quick way to constraint all IO to the same standard? The default for Spartan3 is LVCMOS25 but we want them to be LVTTL. I know I can do it by constraint one by one, but we have several...
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16 years ago
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ML505 : beginners problems
hi, I've just bought the ML505 and I am looking for some examples of VHDL code that I can start to play around with and edit. All I can find are ACE files, which are not that much help to me. I did...
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16 years ago
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Has anyone used Sundance Boards?.
I have a SMT338 board. This is a FPGA module and now I want to add a DDR SDRAM to my system. I have the ucf file provided by the company but in this file I don't find ddr_feedback clock. What it...
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16 years ago
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HI EVERYBODY PLEASE.... HELP REGARDING DDR 2 CONTROLLER
Hi to all i am implementing my own DDR 2 @400 controller my code for BANK AND ADREES lines is while initializing s_ddram_ba
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16 years ago
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Went from Xilinx to Altera: Cyclone-II and I/O pullup?
I'm a longtime Xilinx user, and I've recently switched over to the dark side :) Anyway, I'm new to Quartus-II Web Edition, and I'm trying to port a project from my Xess XSA-3S1000 board to a Altera...
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16 years ago
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VGA signal through breadboard?
Hello, I own a Spartan 3E Starter Kit, which I plan to use for crowd- entertainment purposes. Since the 3-bit VGA output is way too limiting for my project, I am planning to add a 12-bit VGA port to...
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16 years ago
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How can I perform Boundary Scan Testing on Altera Cyclone II FPGAs using JTAG?
I think I have a problem with my Cyclone II FPGA and wanted to do a boundary scan check on the device to see if it is working ok. I looked for options to perform a boundary scan check using the...
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16 years ago
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How to code a bidirectional databus?
What are the rules for coding a bidirectional databus in VHDL? I must be able to connect several different entities to the same bus, and all entities but one has its outputs as 'Z'. Should the bus...
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16 years ago
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Actel timing constraints
I need to write some timing constraints for an ProAsic device. The Designer tool doesn't seem to cater for what I need; as follows: FPGA1 (Xilinx) outputs data on clk rising edge & FPGA2 (my Actel)...
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16 years ago
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ModelSim Memory Content import from Intel Hex
Hello, I'm looking for an import utility from Intel Hex to the supported formats of ModelSim, e. g. MTI or Verilog (Hex). Many thanks in advance Udo
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16 years ago
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Dual Core or Quad Core when running Quartus 7.1
Hello, I'm about to purchase a new computer and I wanted to get some opinions on what I should get. I mostly work with Quartus II on my job and wanted to know what would be a good system to run the...
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16 years ago
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Use BRAM as ROM (Xilinx)
Hi all, is it possible to use Spartan 3 BRAM (on my xc3s1000 it should be 432K) as a ROM memory for data storage or folder mounting under PetaLinux? How to do this under EDK 8.1? Thanks Regards Lancer
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16 years ago
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Quartus 7.1 segv on recent Linux distributions
Although Altera's Quartus II is officially only supported on (by now) rather old Linux releases (SUSE Enterprise Linux 9, Red Hat Enterprise Linux 3 and 4), up to Quartus 7.0, it also used to work...
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16 years ago
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Xilinx 8.2 : Multippass P&R
Hi, I was hoping that someone could point me at a useful document or other link. Our FPGA build flow is currently scripted for a single iteration P&R. Unfortunately, we are now starting to get some...
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16 years ago
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