Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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JTAG fundamentals question
Hi everyone, I tried to figure this one out myself but it turns out not so easy for someone with this lack of experience like mine. I'm writing a PC app that will issue JTAG commands over paralell...
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16 years ago
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MPMC2 + flash bootloader problem
Hello, Does anyone else have problems with MPMC2 + flash bootloader in EDK v9? I started a design on the FX12 mini-module using the ethernet echo server reference design from Avnet. I then added a...
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16 years ago
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Is this the correct way to design FPGA to DRAM interface?
Hi, there I am designing an FPGA to DRAM interface, which uses 160MHz clock. The clock cycle is 6ns, after gate level simulation with DRAM model and FPGA netlist of my design, I realized that the...
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16 years ago
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3rd Annual Opensource Telephony Developer Conference in Chicago, Illinois on June 26 to 28, 2007
3rd Annual Opensource Telephony Developer Conference in Chicago, Illinois on June 26 to 28, 2007 This is to invite your company for our upcoming 3rd Annual Opensource Telephony Developer Conference in...
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16 years ago
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Proper word for total delay?
What is the proper word that describes the total delay in a system from analog input to digital output (including phase shift time in analog and digital filters, calculations + other data transport...
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16 years ago
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accesing JTAG ports on GPIOs
Hi there, I have a virtex II board (xc2v1000), unfortunately no jtag signals are routed on this board (TMS, TDI, TDO, TCK ). This really deprives me from using ChipScope pro on this board to debug my...
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16 years ago
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Atmel FPSLIC users out there?
Hi, In the past I did some work with the Atmel FPSLIC. Eventually the project was changed and the FPSLIC was dropped. I have lots of working code still around from that project. It takes advantage of...
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16 years ago
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SignalTap Analyzer...
Hello, I created vhdl model of risc processor. During simulation it works correctly, but when I programmed and run it on FPGA Cyclone device, it didn't work. So I applied some signals in SignalTap...
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16 years ago
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Quartus-II 7.1 Systemverilog support define `` ?
Does Quartus-II 7.1 support the Systemverilog preprocessor's `` concatenator? `define pori_reg(r) r
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16 years ago
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Best way of moving paralell bits of data from over clock domains?
What is the best way to move paralell bits of data over two clock domains inside an xilinx FPGA (Spartan-3E) to avoid meta stability? By paralell bits i mean for example 10 x 16 bits of data collected...
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16 years ago
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6502 FPGA core
I've implemented a first version of a 6502 core. It has a very simple architecture: First the command is read and then for every command a list of microcodes are executed, controlled by a state...
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16 years ago
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Spartan3 LVCMOS33 Slew rate
I am using Spartan3 LVCMOS33 Open drain 24 mA output driver with 150 Ohm external pull-up to 1.8V. I would like to know the slew rate for both rising edge and falling edge. How to calculate the slew...
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16 years ago
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EDK9.1: XTemac + LwIP + Xilkernel + unistd.h = possible?
Hello all! Has anyone had success using LwIP along with some of the xilkernel functions in a system that is based on the PPC and hard Trimode Ethernet MAC? I keep running into a problem where the...
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16 years ago
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Interfacing EDK application code with Specific BRAMs on FPGA
Hello everybody, I m able to access/write DDR memory through a EDK application. I also want to interface with a ASIC on the FPGA and for that I need to pass the data read from the DDR SDRAM to...
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16 years ago
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PC to JTAG
I read all of the documents I could find about using the JTAG port as a communications interface to the FPGA and implemented my own JTAG controlled logic. The problem is, none of the documents that I...
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16 years ago
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