Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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FIR ON FPGA
Hi, I'm working on implementing an FIR Filter on a FPGA (Spartan 3E), here's what i want to accomplish --> The FIR Filter coefficients are generated on a host system using LabView, these coefficients...
5
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16 years ago
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Cyclone 3 Starter Board Question
Anyone know how the USB Blaster cable loads data to the C3 fpga on the board? The schematic shows a CPLD between the FPGA and the USB port. There is a USB to parallel chip between the cpld and the usb...
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16 years ago
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Can't get AREA_GROUP to work
I am trying to use area_group in my constraints file, but I keep getting the error ERROR:NgdBuild:753 - "constraints.ucf" Line 5: Could not find instance(s) 'gclockInst' in the design. To suppress...
2
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16 years ago
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Seeing DCM LOCKED getting asserted in simulation at the same time CLKDV and CLKFX/CLKFX180 begin toggling
I'm simulating a DCM using Aldec Active-HDL 7.2 with Xilinx ISE 8.2i SP3 simulation libraries and I'm seeing LOCKED getting asserted at exactly the same time my CLKDV, CLKFX, and CLKFX180 output begin...
1
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16 years ago
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Spartan 3E Starter Kit and EDK 8.2
Hi, I'm trying to build and test a simple project for Spartan 3E Starter Kit rev D (S3ESK) board using Xilinx EDK tool and using the BSB wizard. The project is the auto generated peripherals test....
1
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16 years ago
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1 | |
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Chain of LUTs is being removed during par
Hi, I want to test what kind of delay is introduced by having an input go through 1000 LUT1 primitive in a Spartan3E FPGA. I am using ISE 9.1 to synthesize this but during map, it seems that it is...
4
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16 years ago
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Ise Flow with PowerPC
Hi, I am very interesting in how could I use ISE to create a PowerPC model. I know that there is a Export to Project Navigator, but it doesn't seem to work fine. First, I use EDK to create my PowerPC...
4
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16 years ago
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180 differential inputs each 800Mbps using V5
We have an application where I need to feed 160 differential data inputs and 20 differential clock inputs to the high end V5 FPGA. There is one differential clock for every 8 differtnial data inputs....
22
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16 years ago
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22 | |
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Building Gradually Expertise on VHDL/Verilog Design
Hi, i have been reading the VHDL language over the last week and now i want to put what i have learned so far into practice but don't know really from where to start. As such, i am just wondering if...
3
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16 years ago
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ANNC: Secure FPGA Configuration Over Ethernet Webcast
Lattice is holding a webcast tomorrow, Thursday, May 31, "Secure FPGA Configuration Over Ethernet," covering a Verilog / FPGA based design application of a reconfigurable soft embedded microprocessor...
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16 years ago
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XS40 Download Cable
Dear Folks ! I'm hvin a rather outdated XS40 board, which I'm planning to start experiment with. Unfortunately, I don't have the Parallel Download cable for it. Is there any circuitry inside the cable...
2
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16 years ago
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Virtex4 Configuration Problem
Hello, I'm trying to use a slightly unconventional way of configuring a Xilinx Virtex4 FPGA that as far as I can tell should work, but doesn't. The plan involves using a microcontroller to place an...
2
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16 years ago
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Spartan-3E DIG-3E1600 Development Board Kit
Hi, I wonder if someone know where I can buy the "Spartan-3E DIG-3E1600 Development Board Kit" but not from xilinx (says to buy from digilent) and not from digilent (says board not currently...
6
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16 years ago
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Nexys by Digilen xbd file
Hi, I recently got a nexys -1000 board for a project i'm working on and would like to put a xilinx EDK design on the board, however Digilent don't provide a .xbd (board description file) for this...
15
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16 years ago
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Xilinx CIC core in Spartan 3?
Does anyone know if the Xilinx CIC core will work in the Spartan 3? It's not listed as a target (only Spartan IIE) but then the data sheet is dated 2002, wheras S3 apparently was announced in 2003...
1
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16 years ago
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