Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Modular Design Example
Is there an example of a modular design project for ISE that I can download. I could not find one on the xilnx website or included in the ISE examples directory Beyond a picture shown in the...
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16 years ago
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How to guarantee the same relative placement and routing in ISE?
Right now I'm using the ISE 8.2i for an FPGA project and doing simulation with a circuit in vhdl in different locations of a single FPGA. In order to make the compared parameters meaningful, I need to...
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16 years ago
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Bootloader in BRAM to run a program loaded in the DDR
Hi, I want to ask if it is possible to load a program in the BRAM able to run another main program (with PowerPC) in the DDR Sdram. I know this is done by XMD but I would like another launcher program...
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16 years ago
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Cyclone 3 Starter Board connector?
The Cyclone 3 Starter Board has this strange "High-Speed Mezzanine Connector (HSMC)". I'd prefer something simpler, such as a 0.1" header. Are there any adapters / daughterboards available? Philipp
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16 years ago
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CoreGen Issues ??
Has anyone seen an issue with the CoreGenerater that when I try and generate some of the cores I get a "corrupted" dialog box. By this I mean the "image" in the left of the dialog box is jumbled so...
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16 years ago
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ise9.1 : partitions with edif flow
I would like to use partitions with the edif flow. I'm using an older version of SynplifyPro which does not support partitions. From what I understand, the only thing Synplify does, is adding a...
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16 years ago
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using ICAP with the ML310
Hi there, I am trying to use the ICAP module of my Virtex II Pro. I built a project with EDK8.1, but when executing the application on the PowerPC, the ICAP has a strange behaviour. I can successfully...
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16 years ago
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Regarding multiple write problem in opencores pci bridge
Hello there, I have been using opencores PCI core and its working very fine. If someone has already used it please clarify one thing to me. Before I come to the problem let me explain you the setup I...
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16 years ago
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Virtex-4 troubles after configuration
Hi everybody, After successfull configuration of a Virtex-4 my design has troubles. But if I reconfigure using the same bitstream the problem is solved. Did others met this problem? how to solve it?...
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16 years ago
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Xilinx MIG and verifying UCF files
Hi, I just started to use the Xilinx Memory Interface Generator 1.72 and ran into some problems when veryfying the UCF file. - Target xc4vfx100-ff1517 - DDR II SDRAM is MT47H64M16XX-37E When doing...
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16 years ago
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Some doubts in the FPGA design flow in the ISE
Hi, I am not been able to understand the details of the each stage in the design flow. Actually what are the things happening in the mapping stage? During low-level optimization itself, XST infers...
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16 years ago
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Can anyone explain the details of the FPGA design flow in ISE
Hi, I know the the fpga design flow in the ISE tool. But i like to know in more details about the process that takes place in of the stages. Thanks in advance Subin
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16 years ago
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Actel Cortex M1, any info on license fee?
Actel is known lying before, they namly claimed that the use of ARM7 in Actel FPGA is free, actually the FPGA with AES128 that allows the use of ARM7 costs 100 USD more then FPGA without the key, and...
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16 years ago
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s3 starterkit problem
Hi after adding just one GPIO to Xilinx spartan-3A webserver demo design, the system started to fail everything starts up ok, but after setting IP, at the time where lwip should start there microblaze...
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16 years ago
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After PAR simulation, should I assume that it will work on FPGA board?
Hi, I am using ML403 board consisting of Virtex-4 device. I have simulated my design on ISE 8.1i. I completed simulation after synthesis then, Translate, Post-map and Post-PAR. I was getting desired...
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16 years ago
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