Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Problem with System ACE
Hi folks, I am desperately trying to load a design via System ACE onto a ML403 board. What I use: ISE 8.2i ML403 Linux What I did: Synthesized a very small design (some led blinking). Then generated...
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16 years ago
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Create and Import Peripheral in EDK
Hello everybody, I am trying to interface my user logic ip_inv through the OPB in EDK using a register like this: the c code in my test_application to access the ipcore is :...
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16 years ago
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Synchronization of instruction with clock
we are making bram controller which takes instruction from microblaze processor.we have to write a c program giving read and write request to bram anyone can tell us a way to synchronize our...
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16 years ago
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Altera Serial Flash Loader (SFL) question
I just found the Serial Flash Loader (SFL) which allows you to program an Active Serial (AS) part (EPCSx) using the JTAG port, sparing you the need for a dedicated serial config header. According to...
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16 years ago
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Microcontrollers have a better predictable time behaviour than FPGAs
"Microcontrollers have a better predictable time behaviour, because their circuit is integrated in silicon and is unchangeable; unlike FPGAs which have variable timing performances." Is this statement...
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16 years ago
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Raggedstone1 Brackets
For those of you that were desperate for Raggedstone1 brackets we finally have them in stock. They won't show as stock on the shop website for a week or so due to staff holidays but we do have a lot...
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16 years ago
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ngdbuild error : multiple drivers and driving non buffer primitives
Dear all, i am trying to implement a memory controller and am getting the following errors during translate. i wud greatly appreciate if u cud provide some comments/suggestions. thanks,. Mahalingam...
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16 years ago
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FIFO : Synchronous WRITE, Asynchronous READ ?
Hi I have problem to implement a FIFO with "Synchronous WRITE, Asynchronous READ" in Xilinx device. Since the FIFO size is large (more than 48-deep words), I would like to use BRAM or Built-in FIFO. I...
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16 years ago
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Xilinx OPB External Memory Controller
I have a system on a Virtex4-FX with a MicroBlaze and the xilinx opb_emc (v 2.00). I thought I set up the parameters properly to match the async FLASH memory chip that I have on my development board,...
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16 years ago
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LocalLink TEMAC Data Corruption
I have a design using the MPMC2 with a PowerPC and a CDMAC w/ LocalLink TEMAC on a Virtex4-FX. On the ppc I have Linux 2.6.22-rc2 running. The system can ping and simple UDP messaging has been...
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16 years ago
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How to execute application code out of external memory using EDK?
Dear All, Since the program cannot fit in an internal ram, I have to use external memory, such as ddr. As Xilinx edk indicates debugger, bootloader or ACE file should be used to initialize memory...
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16 years ago
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What's the smallest/fastest CLB/Slice/Lut based unsigned integer 64 bit by 64 bit multiplier/squarer design?
I've been looking at the various core/macro generators and they all seem horribly large and slow, almost like student designs. Has anyone seriously taken a good look at hand fitting multipliers and...
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16 years ago
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Weekend pop quiz
A memory block has been told having "read latency of 3", assume the read pointer has been reset How many read clocks does it take to read out the first 10 bytes? How many read cycles does it take to...
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16 years ago
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Tristate ipcore problem with XPS
We are trying to build an ipcore in XPS. Based on the vhdl code we got from digilent's site, we are trying to interface with a graphics lcd on a Nexys. The vhdl code uses an inout port and from our...
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16 years ago
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xilinx parallel cable troubles
Like so many who've come before more me I'm having problem getting th Xilinx Parallel Port cable to work. I know there've been many posts o this issue, but I'm still having trouble. My system is a...
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16 years ago
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