Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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How to Access CompactFlash by using SystemACE?
Hi Guys, I was trying to access CF by using API sysace_fread and sysace_fwrite. I checked xilfatfs library in the software platform settings and #include , but edk still complains....
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16 years ago
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Choosing a clock
Hi I would like some advice on how to decide on the specfication o oscillator required for a Virtex 4 MGT. I have had a look in the use guide and it recommends one by Epson. However is doesnt say how...
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16 years ago
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OPB IPIF Master Attachment
Hello, I am trying to use the OPB IPIF Master Attachment. Does anyone know where I can find a working example of this? Thanks, pk
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16 years ago
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Topics and Ideas for BS Project
Hi friends, I am new to this forum and found that you guys are really helpful to each other with strong knowledge on FPGAs. So I thought to get your help. So I would really appreciate you guys if you...
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16 years ago
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Mesa 5i21 Xilinx
Hi, I=B4m new to card using Xilinx chips. I=B4m developping a new vhd prgogram, and on one Mesa example, at the very beginning of the code, the following statements appear: entity main is port ( --...
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16 years ago
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System Generator installation
Hi, I'm trying to install system generator on MATLAB R2007a. I can't get pass the license agreement as the wizard keep on prompting me for not being able to detect matlab. The message suggests also...
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16 years ago
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FFT and etc on a cycloneII or III help/sugestions.
Hello, I need some advise... I'm trying to find my way for having an FFT running on a FPGA (along with some other easy stuff) Before switching to the option of writing the FFT VHDL myself,I was...
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16 years ago
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XST sythesizes fifos instead of creating black boxes
Hello, I have a weird issue with a Virtex-4 design. The problem is that xst somehow manages to find the coregen fifos vhd files in my design and synthesizes them (I'm using a command line flow). This...
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16 years ago
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modelsim
Hi does anyone already made a tcl command to write down any signals from the wave into a CSV file (excel compatible) thanks for your help jacky
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16 years ago
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MGT Clock
Hi I am designing a board with a Virtex 4 FX20. I want to use 4 out of the MGT devices. I am planning to use a 312.5MHz oscillator for the clock. M question is can I supply the clock to each of the...
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16 years ago
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Power PC heap initialisation on Reset
Hi all, I have a SOC with a Power PC running on a Virtex II pro. On FPGA configuration, the PPC firmware runs correctly, heap reservation on firmware initialisation is correct. When I reset the SOC...
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16 years ago
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ISE and total equivalent gate count
Hi, ISE's map report states a "Total equivalent gate count for design". Can this equivalent gate count be used to compare roughly and very approximate to an equivalent ASIC implementation? Thanks,...
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16 years ago
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Lattice XP2 finally announced
Hi finally !!! XP2 was scheduled for september 2006 so with a little less than 12 months delay its finally announced!! $5F$3F$ Antti
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16 years ago
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any experiences concerning xup and digilent inc.?
I'm student at Chemnitz University of Technology, Germany. I'm interested in purchasing an xupv2p-board from digilent inc as a academic customer (299$). Has anyone done this before (as a student from...
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16 years ago
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TBUF and modular design flow on spartan
I have a project where I am trying to use modular design flow. When I do synthesis of one of my modules I see the message in the log. Number of TBUFs: 61 out of 0 (*) I think this is causing me...
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16 years ago
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