Latest threads in Field-Programmable Gate Arraysshow only best voted threads
| Subject | Author | Posted | Replies | |
|---|---|---|---|---|
|
|
another Forth CPU design
While trying to minimize my microcode implementation to implement a small 6502 CPU, eventually I designed a new Forth CPU: I would like to have a full Forth system for it, which could run at about 4...
6
|
16 years ago
|
6 | |
|
|
LVPECL output skew
I would like to use Virtex5 FPGA to output 16 differential channels at 800Mbps source synchronously. I am planning to use bufio to minimize the clock skew internally. Bufio has about 50ps skew on the...
15
|
16 years ago
|
15 | |
|
|
How can i convert char* / string to sc_lv<16> ?
Hello, i am beginner in SystemC and have to programm a lawa simulation. My Problem is, i have to read the commands from a file in the following form : 8 * 16 Bits: 1111111111111111 0000000000000000...
—
|
16 years ago
|
— | |
|
|
Symbolic names for pll derived clocks in SDC file? (quartus)
Hi All, I'm synthesizing the IP core for my chip using the Altera Quartus tools. When I define constraints in the SDC file for the Timing Quest analyser & fitter, I use the derive_pll_clocks command...
4
|
16 years ago
|
4 | |
|
|
What's wrong with CoreGen 7.0: dynamic coef multiplier (port B = constant /w reloadable)
Hoping that the dynamic constant multiplier could save numbers of CLBs, but it's contrary. So, what's the use of it if it takes more resource than the true parallel multiplier? Here's the settings for...
5
|
16 years ago
|
5 | |
|
|
Lattce SC Purspeed I/O
The Lattice SC purespeed I/O supports 2 Gbps data rate. This is the maximum available data rate in parallel I/O - in comparison to Altera and Xilinx. I would like to know how well designed Lattice SC...
8
|
16 years ago
|
8 | |
|
|
JTAG as UART for PowerPC in XMD.
Hi, I have seen about configuring the JTAG as UART since I have not RS232 port in my board. I have found that Xilinx provides OPB_MDM as uart with C_USE_UART PARAMETER, but in my desing I use PowerPC....
4
|
16 years ago
|
4 | |
|
|
verilog HDL problem
what is the error in the following code. in it the main module is "test". in that module's "always" block another module "counter" is called. but it shows error. how can i solve the problem? how can i...
2
|
16 years ago
|
2 | |
|
|
A first FPGA project
I have been trying to find the time to start a project with an FPGA for a while and I think I've finally found one. I've messed around with my Digilent FPGA development board but I have never created...
6
|
16 years ago
|
6 | |
|
|
No output while booting ML403 board
Anyone, When I try to boot linux on a Xlinx ML403 board I get the following out put: loaded at: 00400000 004FA1A0 board data at: 00000000 0000007C relocated to: 0040405C 004040D8 zimage at: 00404FE5...
2
|
16 years ago
|
2 | |
|
|
FPGA / Virtex II Pro / LWIP
Hi, I'd like to get some help from experienced people because I'm really running low on ideas here.. I'm a beginner in FPGA/LwIP and I can't seem to make it work using Xilinx EDK 8.2i. I've been...
4
|
16 years ago
|
4 | |
|
|
How many OSERDES per bufio
It seems that bufio has the lowest clock skew in order to clock the oserdes. OSERDES in my configuration requires two clocks 1x clk and 2x clock. I would like to know how many OSERDES can I drive...
3
|
16 years ago
|
3 | |
|
|
What should be taken care of when two FPGA broad connected together?
I have two FPGA development boards, using different power source. when I connected their IO pins, should I connect the GND of board too? I hesitate to do that because I am not sure if these two GNDs...
4
|
16 years ago
|
4 | |
|
|
ANNC: PCI Express Card Power Management Webcast Today
Lattice is holding a webcast today, Wednesday, June 6, "PCI Express Card Power Management." The presenter will be Jim Krebs, from our programmable mixed-signal applications engineering group. If...
—
|
16 years ago
|
— | |
|
|
Quartus Advisors
Hello, I use Altera's Quartus II software for my FPGA development and in the software package they have the following Advisors: Timing, Power, Resource Optimization, Increment Compilation. I usually...
1
|
16 years ago
|
1 |