Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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synthesis translate_off
Does anyone if "//synthesis translate_off" in Xilinx is also honored by ASIC synthesis tool (Design compiler) ? Thanks
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16 years ago
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SystemC - Libero IDE
Hi all, just for curiousity anyone knows if Actel is working on some tools to include SystemC synthesis in the future for their Libero IDE? This would be a great advantage for some of their developers...
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16 years ago
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Rocketio connection Virtex2pro-Virtex4
Hi everyone, Could someone with experience or simulation tools provide information on the hardware requirements to interconnect Virtex2pro and Virtex4 with rocketio at 2.5Gb/s. The simpler the better,...
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16 years ago
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Could I use the opencore ddr_sdr core (for SDRAM) in Xilinx Platform Studio (C code)?
If I download ddr_sdr core from Opencore, how could I use it with PowerPC or Microblaze to access memory with C code. Is it enough to load this core in c:EDKhwXilinxProcessorIPLibpcores? But I need to...
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16 years ago
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How do i add my IP to EDK?
Hi, I have designed a IP core, how can i add my IP to EDK? Anyone who can help me?
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16 years ago
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spartan 3A : DDR2 controller
for edu. purpose, I would like to modify s3astarter_ddr2 design to use it with picoblaze (store some data to ddr2 and read them back later). I understand I have to hack vhdl_xst_bl8_ddr2_test_bench_0...
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16 years ago
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XPower: Can't change activity rates
Hi, I have created a .vcd file using modelsim and am trying to estimate the power consumption for my design. The problem is when I load this vcd file in the XPower it gives warnings as shown below....
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16 years ago
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V5 GTP Sim Problem
I am trying to simulate the V5 GTP in ModelSim SE and am having trouble. I have compiled the sim libraries, followed the directions in the GTP user guide, followed the directions in the Synthesis and...
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16 years ago
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.xco file and vcs verilog compiler
I have a Xilinx design that uses mainly verilog RTL and some .xco file for coregen FIFOs and such. I am using vcs compiler from synopsys. This compiler does not recgonize the xco files. Is there any...
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16 years ago
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want to pay for DCM active phase shift controller.
Hi all, I've been debugging my Active phase shift controller for so lon and I think it's time to ask for help. If you have done this and woul like to make some money, please reply me and let me know...
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16 years ago
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Help needed regarding addition of Custom IP core to EDK
Hey Folks , I face a strange problem of adding my custom IP to the EDK project . My custom IP has two parts : a Small FSM and a Fifo Generated using coregenerator ( This was generated as EDN and the...
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16 years ago
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No serial output while booting a Xilinx ML403 board
Hello, I am new to the embedded world and I am having a problem getting a Xilinx ML403 board to output any info while it is booting. I am using EDK 9.1 from Xilinx to create the bit stream for the...
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16 years ago
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Enumerated type simulation issue (ISE simulator, 9.1.03i)
Hi everybody, I'm having trouble simulating a state machine with ISE simulator (ISE 9.1.03i on Linux). At this point I'm not sure if the issue is in the simulator itself or in the waveform viewer...
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16 years ago
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Tecis-Termin
Hast mich ganz sch=F6n geweckt heute morgen... wenn Du so lange snoozed und nicht raus kommst werd' ich wach. Ich hab' uns f=FCr Mittwoch 11.7. um 19:00 einen Termin mit Herrn Rolf Maier-Dammann...
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16 years ago
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how to assert PSEN for DCM
Hi all In the datasheet, psen has to be asserted before rising edge of psclk fo one clock. How can I implement this? Should I use the clock to driv psclk as the clock of my state machine? If so, then...
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16 years ago
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