Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Substitute for FORK / JOIN?
Hi guys: I'm writing a program in Verilog where I need for several blocks of code to execute concurrently (parallel blocks). I used the "fork - join" command which should do just what I want....
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16 years ago
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corgen cic = terrible efficiency?
I'm working with the xilinx corgen cic v3.0. I'm finding that to get a decent rejection in the images (60 dB) I need about 4 stages. My input is only 10 bit and I still end up with a 66 bit output, 50...
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16 years ago
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How to create simple design?
I have installed the xilinx ise 8.2i. I want to make a simple design for test. I created a schematic project and added "and2" . I want to compile this project and program it to cpld, so one pin will...
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16 years ago
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|!|!|!|!|!|!|!Sparten 3E : !!!USB 2.0 Driver in the FPGA!!!|!!|!|!|!|!|!|!|!
Hi Programmers this is my first time to join the Forum I'm a senior student in the University of Jordan of Computer Engineering Department My question is that we know that the EDK tool is like a small...
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16 years ago
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Reshipping spartan3 PCIE board to England
Apologies if this is a bit too off-topic for the list, but I'm guessing other Englanders (and other nationalities for that matter) have similar issues. Anyway, I really want a PCI-E spartan board, and...
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16 years ago
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Xilinx DFS woes
Hello, I have a oscillator with 16 MHz connected to a gclk pin of a Spartan 3E. Inside the FPGA , I use the 16 MHz clock and a clock generated by multiplying the 16 MHz with 8 with a DFS. The code is...
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16 years ago
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Has anyone seen a vxWorks driver for the Xilinx LL_TEMAC?
Any information on the subject will be highly appreciated. Thanks, /Mikhail
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16 years ago
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Cadence TestBuilder
Does anyone have a copy of the last release of "Cadence TestBuilder"? I would appreciate if you can give me a copy. -- Amal
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16 years ago
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How to deal with unavoidable setup time violation in CoolRunner II cpld?
Hi, I apologize if this question is too stupid... basically I want to build a protocol analyzer with a CoolRunner II cpld. the CPLD will watch the bus line and extract data. I have passed behaviorial...
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16 years ago
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is Ultracontroller-2 supposed to work under XPS/ISE 9.1?
Has anyone had success making ultracontroller-2 work under XPS 9.1? When I tried opening uc2_1ppc_v4_vhdl/uc2.xmp project file under 9.1 XPS it says "we recommend that you exit XPS now. As a project...
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16 years ago
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Agilent Dynamic Probe?
It's time for a new scope, and I'm thinking of getting an Agilent MSO6000 series, in part because of the FPGA dynamic probe capability. Anyone here used that? How well does it work? Thanks Pete
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16 years ago
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Virtex 5 Rocketio
Hello folks, I am using the V5 rocketio to implement a high speed serial IO. I have configured the GTP and it works , but the only problem is that the first 5 words ( comma and data) are corrupted at...
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16 years ago
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Nios II problem
At work I'm using a Nios CPU with Quartus 7.1. I've configured it with 512 bytes data and instruction cache, and it uses internal RAM. I have a struct like this: struct Something { alt_u16 foo;...
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16 years ago
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Modelsim simulation Q
Sorry for this newbie-like question, but I can't remember how I did it before for the life of me. Normally I pre-select certain signals before I run the sim, and look at those in waves. The problem...
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16 years ago
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Does anyone modify the opencore ddr_sdr for DDR Sdram for internal feedback?
I know this topic has been already treated but at the moment I have no solution yet. Is it possible to edit this opencore so you could use internal feedback?.
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16 years ago
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