Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Change PicoBlaze ROM Code on Spartan 3E Development Board
Hello everybody, do You know how to change the program of an existing PicoBlaze implementation on a Xilinx Spartan 3E development board? The board uses an USB cable to download the bitstream to the...
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16 years ago
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Unbuffered jtag programmer?
I tried the unbuffered jtag programmer, it is partly working. It allows me to go into the device with impact and select various command. For exmaple I can get the device id or checksum, but when I try...
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16 years ago
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Rocket IO clocking
I have a problem with the RocketIO component. The documentation says that I need a differential clock for the Rocket IO. I am using Xilinx EDK 8.2. The input frequency is 100 MHz. The bus frequency is...
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16 years ago
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Question about xilinx jtag programmer
Does anyone know what it means pinout compatible to UFS / Twister / N-Box / Power Flasher & Other compatible gsm interfaces. Where do I fins this pinout?
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16 years ago
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Add DMA support to a custom core?
Hi everyone. I have a core to control a I/O peripheral. This core is based on a FIFO to get words from a I/O bus (32 bits). But now, I want to read from the FIFO and copy the words to the BRAM. I know...
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16 years ago
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Simulation problem
Hi all, I wrote a generate loop to generate a switching logic. I am getting the expected circuit from the synthesizer(synplify). But it's not working in the simulator ( Modelsim ). The code is like...
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16 years ago
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Unable to use xmd or mb-gdb with microblaze cycle accurate simulator target
Subject: Unable to use xmd or mb-gdb with microblaze cycle accurate simulator target Hello: I am trying to use gdb and xmd to connect to the cycle-accurate simulator target on microblaze but have been...
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16 years ago
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USB full speed final project proposal
I invite you to use free code of a USB full speed project as final work for diploma. The site includes some description of the functionality and main state machines. The code is based on some free...
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16 years ago
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Hobbyist trying to decide which device to start with...
I've spent several hours browsing the Xilinx site (and not so much less the Altrera site), and I'm starting to get some idea of what all the different device families are. However, after digging...
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16 years ago
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Spartan-3e JTAG no device id
I am trying to get an xc3s250e-4tq144c to configure using JTAG. 1. impact reads 0x00000000 as idcode This causes impact to error out during identify with a strange error about missing bsdl's 2. JTAG...
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16 years ago
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MPC 8321E DDR2 interface
i am using MPC 8321E POWER PC ,can any one tell me how to interface 2GBYTE DDR2 SDRAM. problem is it has only 32 bit data bus. regards anand
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16 years ago
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Xilinx DCM Reset
I have been reading through UG331 for information on the DCM, especially in the case with external clock feedback. On a previous project we used a Microblaze with an SDRAM controller, but did not have...
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16 years ago
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DIFF_TERM Question
For a Xilinx V4, there is an IBUFDS_DIFF buffer that you can use in the I/O pad. However, it appears that there is no differential termination resistor available for this setup. In XAPP861, it shows...
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16 years ago
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Metastability in very slow clock domains
Hi, Lets say we have a signal crossing from a high frequency clock domain into a low frequency clock domain, where the low frequency domain frequency is very low, say 32kHz. Is there any point in...
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16 years ago
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Microblaze and software interrupts?
Hi all, I'm developing a multicore system with up to four Microblaze cores. Now I'm searching for a solution to inform the cores about e.g. messages with a software interrupt. That means, one core...
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16 years ago
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