Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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New with FGPAs
Hello, I've just started a small project with a Xilinx Virtex 4FX board. In general terms my objective is to read various data over a Gigabit Network, manipulate them, and then transmit them back to...
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16 years ago
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I need relocate my program outside bram...
I'm developing an embedded web server into a XupV2pro board with a VirtexII-pro fpga. While all my code was in the bram memory all works fine, the problem was that the application grew and grew until...
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16 years ago
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Xilinx ISE, EDK and some ground roules in software development
Hi, I started to learn ISE and EDK 9.1i, but I spent much much time to get things running because they did not work as described in the manuals. Now I write this posting in the hope that someone from...
15
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16 years ago
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USB analyzer evaluation
hi all experts could you recommend good USB analyzer for me i am an new USB driver developer and my boss wanted me to investigate which one is the best choice 1.support 1.1/ 2.0 / OTG specification...
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16 years ago
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Multiple Core generator MAC FIR Filter 5.1 Cores
Hello all, I am trying to generate several MAC FIR Filter cores for the same project. The filters range in length from 32 to 63 taps. I do not have any problem generating the core, but have noticed...
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16 years ago
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Doubt in Asynchronus Circuit design
Hi All, I am designing my first real clock domain crossing circuit. My problem is a high speed wrapper for a low speed device. What is the general approch to be followed. I will tell you my approch...
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16 years ago
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Spartan-3A: 200A & 400A Image problems / variance...
Hello Group. Having a home-made PCB board which can adopt to both Spartan-3A XC3S200A and XC3S400A FPGAs in the same FBGA320 footprint, we are having great troubles getting the 400A image of the logic...
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16 years ago
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Does synplify 8.8 can support xilinx virtex5?
I use synplify 8.8 to synthesis my design. And my design contain xilinx ip core (generated by core generator). My design can be synthesis with XST. But when I use synplify 8.8, synthesis cannot be...
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16 years ago
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Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
Hi everyone, No doubt this subject has been discussed on numerous occasions: ?lnk=st&q=microblaze+vs+nios&rnum=3#6916d47ebb3868b1 However it seems that it has been a while since the subject has been...
44
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16 years ago
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Power PC Reference Design timing failed
Recently, I download a reference design from Xilinx. Then implementate in EDK9.1.02i, while checking the timing report,I find some fails,such as:...
1
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16 years ago
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Xilinx V4/V5 FPGA SATA GTP
V4 FPGA has independently RXSIGDET port signal,but V5 not. how to detect the signal on V5 GTP?
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16 years ago
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Can't get Actel tools to run on SL4.4 (RHEL 4.4)
Has anyone been able to get the Actel Linux tools to run? I wasn't able to install them on CentOS5 so booted into Scientific Linux 4.4 (a RHEL 4.4 clone). Installation went fine in 4.4 but I haven't...
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16 years ago
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ICAP in V4 FX20 only working after Reset
Hello, I am trying to use the ICAP module of a Virtex-4 FX20. I built a project with EDK8.1 using the OPB-ICAP module from EDK 9.1.2. My configuration is a basic microblaze system with the usual...
3
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16 years ago
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LVDS via Emulation
Hi all, I've just read something about LVDS via emulation, in the datasheet of the FPGA its specified that some banks natively support LVDS while some other banks are specified to support LVDS in...
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16 years ago
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read/write in bram block
Hi all, i am designing a system in which we have a bram block,microblaze processor and other essential component. i have written a verilog code for bram controller (successfully compiled)to interface...
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16 years ago
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