Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Re: ESR Meter - Roll your own - ESRrev0.JPG
I'm looking for something that will be fast and easy to decode at fpga config time. I just did some statistical analysis of a bunch of existing Spartan 3 bit streams. If you treat them as bytes, and...
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16 years ago
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LiveDesign, Altium [opinion]
Hi, Does anyone have experience with Altium LiveDesign (Xilinx Spartan-3 XC3S1000) ? How does it perform with ISE WebPack, are there any odd issues with it? Any comment will be appreciated. I would...
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16 years ago
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Question on Virtex2p DCMs usability
Greetings, First off, let me share with you that I'm a complete newb when it comes to FPGA/ISE/VHDL. I'm using the "free" version of ISE and my end device is a V2P-7 672 pin FPGA with the pins already...
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16 years ago
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fifo counter in virtex-4
I use ise9.1 and synplify8.4.2,I use the core generator to generate a fifo,the parameters as follow,different clock and different data bus widths,write 16 bits and read 128 bits,now I want to use the...
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16 years ago
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ML555 SFP module
I use Xilinx PCSPMA GTP IP core to connect ML555 SFP interface. But how to connect the signal_detect signal of PCSPMA GTP core to indicate presence of optical input?
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16 years ago
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XilinxSystemGenerator and Simulink
Hi, I've been working on a simulink model built using the Xilinx Blockset to try to verify the function of an interplation filter made from the MacFir Core. The full working VHDL version of the...
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16 years ago
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XPS 8.2 "UPDATE Tcl procedures"?
Hi, all. Can anyone tell me what "Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC..." means, and what platgen actually does to the .tcl files? I'm wondering if this could be the...
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16 years ago
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verilog code for read write in Bram block
Hi all, i am designing a system in which we have a bram block,microblaze processor and other essential component.i have written verilog code for bram controller .i have to call this verilog code by a...
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16 years ago
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or1k binutil source checkout problem
i've checked out the binutils for or1k from the downloaded files contain two files with .diff extensions. it does not download most of headers and implementations files. Please let me know how to use...
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16 years ago
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multiprocessor design-shared memory-howto
I'm dealing with a multiprocessor board design. The major issue is speed. Processors should be connected to a ring but they don't have dedicated ports (similar with Serial Rapid IO on TI DSPs see here...
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16 years ago
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sdr woes
Hi all, I am trying to build a sdr to demodulate am signals. i am using xilinx dds to generate my local oscillator signal. when i do simulations in matlab using an ideal cosine waveform everything...
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16 years ago
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Debugging in EDK
Hi i am debuggin a simple program running on the Spartan3e starter kit : int main() { int k = 3; int i = 2; int j = 4; i = k; i = j+j+k; while(i < 15) { j--; i++; } return 0; } The problem is that the...
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16 years ago
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or1200 uses more than 100% of resources. how to reduce?
i've synthesized or1200 and it consumed 3920 slices and 7258 LUT's which are beyond what is available with my xilinx device with 400K gates. (I followed instructions ghiven in "openrisc-HW-tutorial-...
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16 years ago
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ML555 SATA GTP dosen't work
My SATA host controller includes TX/RX OOB Sequence generation ciruit(it can generate COMRESET/COMINIT/COMWAKE). My GTP setting is as following, a>GTP clock:150M,Gen1 mode,8 GTP;...
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16 years ago
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ML501 Constraints file problems
Hello, I'm testing ML501 board, very nice. On the Xilinx site the documentation of this board has some errors like the constraints file(...also unavailable...). Looking the EDK example design I see...
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16 years ago
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