Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Help with Libero IDE and Verilog...
Hi all, I recently purchased the Actel Fusion Starter Kit. I'm new to both Libero IDE and Verilog and was hoping for some guidance. All I'm trying to do is turn LED D1 on when the voltage from the...
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16 years ago
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CML output swing for V5
I am using V5 GTP. As per my understanding, the GTP output should swing between 1.2V and 700mV and common mode voltage of about 950mV. But when I look at this using oscilloscope, I see that the GTP...
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16 years ago
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Convert Schematic Files (.sch) to Verilog Files (.v) for simulation in ModelSim
Is there a way to convert a schematic file (.sch) into a functional verilog module (.v/.vf) from the command line? I want to do this so I can compile the resulting verilog file with modelsim for...
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16 years ago
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Xilinx PCIe endpoint core minimalistic design
Hello, I am implementing a PCIe design for the HiTechGlobal HTG-V4-PCIe60 (Virtex 4 FX60 and FX100) board and having a little difficulty. What I'm trying to do is create a minimalistic base design...
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16 years ago
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Re: Designing the right clock tree for a multi-FPGA setup
Hi - Can you tell us a bit more about your requirements? In particular: - What clock frequency are you distributing? - What are your synchronization requirements? - Do you plan to have synchronous...
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16 years ago
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ASM within C code in a PPC405 of VIRTEX II Pro
Hello, I would like to know how to put ASM instructions in a C code. With a G5 you can do that kind of functions: asm long MyFunct(int a, int b, *pt) { fralloc mr r6, a //r6 has a mr r7,b //r7 has b...
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16 years ago
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Flex 10k100 & EPC2 redux - forgot the special ingredient?
I posted last year about a strange problem I was having with a Flex 10K100 board. At one time, I figured out how to setup programming files so that the EPC2 would correctly configure the FPGA....
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16 years ago
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Chipscope 9.1: Any easy way to rename and regroup signals?
Hi Xilinx Killers, It is really annoying to rename and group all the signals everytime when design is modified and new bit file is used to configure the fpga. Anybody knows how to avoid renaming and...
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16 years ago
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New board JTAG error
Hello every one, We have designed a board which contains an ALTERA fpga and an EPROM(EPC2LC20).The design is done with respect to some existing reference schematics.We have populated our PCB so as to...
2
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16 years ago
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Altera MAX III Status ?
Does anyone know the status of the promised Altera MAX III CPLDs ? These were supposed to roll out early in 2007, but they are now not even registering on any Altera road-maps ? Has Altera pruned...
5
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16 years ago
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MiG : Memory Interface (DDR SDRAM) as an ISE schematic symbol
Hi, I am trying to use a Memory Interface generated by MiG (Memory Interface Generator 1.72) as a symbol in a schematic based project. CORE Generator doesn't allow me to select schematic based as a...
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16 years ago
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Strange warning message from ise8.2i ?
I have received the following error warning: Cpld:828 - Signal '' has been minimized to 'GND'. Waiting with antissipation, Thanks
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16 years ago
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Type Conversion in VHDL
hi all, how to convert integer numbers to real numbers and vice-vers. and what will be the hardware generated for real multiplication. please reply soon ... thanks
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16 years ago
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Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
Well it's not new at all, but I've just discovered Yet Another Open Source RISC core -- Lattice's Mico32. It comes with GNU tool-chain (making the software-development side similar to OpenRisc 1200?)...
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16 years ago
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SystemC in modeling HW/SW
Hi, I was told by a friend that SystemC is currently the best to modeling hw/sw design. I've read on the internet where people were saying that SystemC is a more "complete model" which I don't quite...
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16 years ago
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