Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Library unit VPKG is not available in library UNISIM
I am trying to synthesize a code using ISE which contains a component fifo the fifo code is the following -- synopsys translate_off library IEEE; use library UNISIM; use use entity ifo is...
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16 years ago
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Using the EDK based video decoder
Hello everybody, I am trying to capture input video data using the Digilent Video Decoder board (VDEC1) connected to the Xilinx XUPV2P board. I am trying to use the EDK based example provided by...
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16 years ago
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Interfacing the EDK based video decoder
Hello everybody, I am trying to use the EDK based video decoder design provided by Digilent. But when I am trying to buid the netlist I get the following licensing error from the FLEX . I have...
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16 years ago
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Xilinx XST 9.2i.01 - still incomplete support for always @*
After waiting patiently for Xilinx to support always @* properly, I'm still having problem with this code: localparam integer D_W = 32; localparam integer DEPTH = 512; reg [D_W-1:0] memory...
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16 years ago
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Enterpoint Web Site
Due to server maintainence our website by our hosting provider and email went down last night. After over-running it's all back now. Apologies to anyone disappointed in trying to obtain downloads...
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16 years ago
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modelsim Warning "VIOLATION ON D WITH RESPECT TO CLK"
In modelsim Actel, when I do the post layout simulation, I have a lot of warnings. =BFhow i can take off the vitalglitch error (no the glitch) to can see other errors? I have other warning in the .log...
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16 years ago
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libero.actel
Is possible force the assignation of a number pin (no global pin) to a clock? (=BFcan i do before synthesize?) On synthetize put me the clock in a global pin, and before that, on compile, on layout I...
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16 years ago
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regarding specifying clock as internal signal in chipscope
Hi all, i am using chipscope for checking the behavior of the internal signals, i have a problem my differential clock and data input is coming form the other board. i am just taking the differnential...
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16 years ago
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JTAG detection
Hello Every1! I am facing one problem and would like to seek help from you people. We have designed one board where "EPF10K30ATC" FLEX10K family FPGA and serial PROM "EPC2LC20" are being used. When we...
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16 years ago
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Bypass caps for Spartan 3, PQ208, 4-layer board... Educational Project
Greetings, all, I have read through many postings about bypass/decoupling capacitors for Xilinx FPGAs at It seems to me common "solution" (there are many, I'm sure) to use at most 10 or 20 caps for...
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16 years ago
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Can multiple Ferrite Beads be used to connect ...?
I am designing a board. I splited the ground plane into one analog plan and one digital plane. Can multiple Ferrite Beads be used to connect th both planes or only one FB should be used? In some...
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16 years ago
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BD file generation
HI all, how to generate a buffer descriptor file having filelds: Host address,transfer size,Target address and next pointer... suppose if i want to tranfer 1MB from host memory after having splitted...
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16 years ago
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Actel. Libero. Synplify: "unbound component..."
when I synthesize the FPGA (ProASIC PLUS) in Synplify of Libero I have got a lot of warnings: "Unbound component (DFF or AND2...) mapped to black box". It seems that don't recognize the basic...
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16 years ago
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How do I use Lattice Mico32's debug-engine on a non-Lattice FPGA?
I've figured out how to compile the RTL in Xilinx ISE Webpack9.2i and Altera Quurtus II 7.1. (It just took a few simple RTL-edits.) But what about the JTAG-debug unit? It seems to use the Lattice's...
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16 years ago
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DDR SDRAM in extended military applications
Hi, I am wondering what kind of issues I should look for when designing in DDR SDRAM for extended temperatures. For e.g. does temp. compensated refresh cycles extend to ambient temperatures of -40 to...
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16 years ago
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