Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Help on TRB_DC2 Camera module interface
I am tring to design a video acquisition system. I am usimg the DE1 borad and the compactable TRB_DC2 camera module with it.().The problem i am facing is on the data sheet 20 pins are assigned to each...
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16 years ago
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Question on using RLOC_RANGE
Hi all, I am trying to tell the ISE tools to place DSP48s belonging to a complex multiplier (generated with coregen) close together in a V4FX chip with the following line in my UCF: INST...
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16 years ago
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Odelay usage in virtex5
I would like to use Odelay primitive to delay a signal generated in the virtex5 fpga fabric. For this I am hoping to use IODELAY as shown below. mlinit_in_l is the signal I would like to delay it in...
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16 years ago
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Microblaze Interrupt Handler
Hi All, I'm beginner for Microblaze. I use Spartan3E eval kit. I want to create custom ip and use interrupt. 1 - I create custom ip, connect it to OPB then I connect ports. I'm trying my ip on the...
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16 years ago
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Simple UDP packets forwarding using lwip sockets
Hello. I have just started working with a Virtex 4 board, and I need to make an application which will be connected on a Gigabit LAN using its hard TEMAC, collect some data transmitted to it (at...
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16 years ago
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Xilinx something happening with Spartan-3?
hi I wonder how come is xilinx website at least partially broken whenever I need something? today as example Spartan3 page is JUST EMPTY page? It is not possible to belive that a real webmaster would...
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16 years ago
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Open position at The MathWorks, HDL Applications Engineering
The MathWorks at Natick, MA has an open position for an HDL Applications Engineer. If you are interested in this position and would like to learn more, please send your resume to AT
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16 years ago
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Restricting XST parameter widths from .mpd files?
I'm working with a custom verilog core that accepts a small number of parameters, and I'm having a hard time pushing them through XST properly under EDK 8.1. For example, I include the following line...
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16 years ago
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EDK 9.1.02i warnings flood
Hi! I recently installed EDK 9,1.02i. When I synthesize a project I get thousand of warnings, which is really annoying: WARNING: vhdl is not supported as a language. Using usenglish. Reading the real...
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16 years ago
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query in byte blaster/signal topic logic analyser
Dear All. I want to see the signals in the EP2C12Q240C8 FPGA for my design inside with several instances..It has EPCS4 configuration device .I am using quartus7.1 s/w.I am using byte blaster II...
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16 years ago
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spartan-3e spi problems
Hi, I am having trouble configuring a xc3s250e from a st m25pe20 spi flash rom. Originally init would not go low and the chip was constantly looping through the config. I inserted a 256 0xFF's at the...
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16 years ago
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Xilinx MIG DDR2 initialization problems
I have used the MIG 1.72 tool to generate a memory interface for the DDR2 SODIMM on the Xilinx ML501 board. It works... sort of. I The SIM_ONLY parameter, which disables the 200us power-on delay for...
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16 years ago
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Can Altera and Xilinx Done signals be tied together? Has anyone done it?
I've got a situation. My software is saying that my two Altera Stratix II FPGAs are successfully programmed, but they don't appear to be. I think something may be erasing them as soon as they're done...
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16 years ago
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Question about GSR?
Hello, What does GSR pin do, when should I use it? How do I use it? Is it required in every design? Thanks in advance for any response.
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16 years ago
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V5 Differential Select I/O
Xilinx V5 supports Differential select I/O data rate upto 1250 Mbps. It supports HT_25, LVDS_25 and may other electrical standards. What electrical standard should be used to support the maximum...
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16 years ago
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