Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
Writing data to bram with microblaze
Hello, I have a microblaze design which includes two bram with microblaze' bram. I want to write the addresses of dip_switches to second bram.How can write this code in Xilinx Platform Studio SDK?...
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Static Timing Analysis Using Primetime for FPGAs
Hi, Has anyone recently done a comparision of the utility of Primetime vs. Xilinx or Altera timing analysis engines? Anyone have an data to support if Primetime actually catches more static timing...
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help on basics of ethernet interface
hi all I am a newibe. i am tring to send bit stream data through ethernet. i am using altera DE2 board. i have my data in SDRAM and interfaced onto the etherenet pin by avalon switch fabric. The...
 
Xilinx Webpack for Linux 64 bit?
Does there exist a 64-bit Linux version of Xilinx Webpack? I see the programming tools are available for Linux as 64-bit... When browsing the Webpack service packs, there is a 64-bit Linux service...
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Fatal Error ISE 9.1
hi, i get this message when i run "map". Using target part "5vlx30ff324-3". Mapping design into LUTs... Running directed packing... Constraining slice packing based on guide NCD. Running delay-based...
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Slow PSDONE when using variable phase shift with a Spartan3E 500 (stepping 1)
Hello, We have implemented a variable phase shift in a spartan 3E device. The phase shift can be set with a register. Normally the PSDONE signal should go high when a phase shift is performed. This...
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Altera Cyclone II and Cyclone III "distributed" RAM?
I looked on Altera's website, but I could not find any description on how distributed (LUT-based) RAM works on the CYclone II/III family. FOr the Stratix III, I see Altera called this feature "M-LAB."...
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Xilinx Webpack 9.2 and Windows 2000 Pro?
On Xilinx's website, Webpack product-description no longer lists Windows 2000 as a supported O/S. I'm currently using Webpack 9.1i.03 on a Windows 2000 machiine. Will I have problems if I try to...
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regarding RTOS in NIOS II
hi everyone i am trying to use RTOS in NIOS processor. After going through its documentation i found that UC/OS2 and UClinux are the two versions avaliable. I am interfacing my design to a Ethernet. i...
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Upgrading from EDK 8.1 to EDK 9.1i
Gang I purchased the MicroBlaze Spartan 3E Development Kit. It comes with a copy of the the EDK 8.1 and uses ISE 8.1 Webpack. I would like to load the EDK 9.1 and ISE 9.1 Webpack on my machine. I am...
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ASIC Digital Design Blog
Hi All, Please allow me to shamelessly plug my blog. It is relatively new (2-3 months old) and just passed the 5000 views mark. I am blogging about a lot of topics that might interest people here....
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DDR Simulation Model
During my work with the XUP development board another problem occured when I tried to use the on-board DDR-SDRAM. A data stream is written into the RAM using the PLB bus and burst mode (16 x 64 bit)....
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Xilinx/ModelSim bug ? Clocking headache ...
Hi every one, I had a problem this morning in a functionnal simulation that I finally traced to the unisim library. Basically, internally they do : prcs_clk: process (clk) begin if (clk'event) then...
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V5 compared to V2P
I'm looking to update a couple of products from VIIPro to V5 devices. Is there some very rough comparison of the relative logic capabilities of the 2 FPGA ranges somewhere? The redefining of the logic...
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Looking for PLD with embedded memory
I'm looking a PLD with 5V TTL-compatible I/O that has ~2Mb of integrated memory that can be used as ROM and ~64Kb of integrated memory that can be used as EEPROM. Initially I considered using a...
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