Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Synthesizing fixed_pkg in ISE 9.2
Hi, I'm trying to synthesize a design with the fixed_pkg package in Xilinx ISE 9.2. I'm using the version adapted for Xilinx from Compilation works fine, but after that I get the following, not...
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16 years ago
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Specifying LVDS I/O's in Xilinx FPGA's
Hi, Can someone please point me in the right direction. I attempted to define my LVDS inputs via the UCF file for my Xilinx spartan xc3s1500. NET data_in LOC = F19 | IOSTANDARD = LVDS_25 ; the Xilinx...
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16 years ago
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Write of 64 from PowerPC to my IP conected to the PLB?
Hello, I have designed a IP Slave connected to the PLB bus. My IP Slave to the PLB is a Bus bridge which connect the PLB to another Bus and a Coprocessor connected to this other Bus. My second bus...
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16 years ago
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Exception handling code in the OR1200
Recently, I read the source code of OR1200. But I am a little confused about the Exception part. When a exception occurs, the correct execution PC value is found and stored in the "epcr" register. And...
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16 years ago
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Mico32
G'day (o; As I started development on the Mico32 DSP board I've setup a site concentrating on my current work: - u-boot bootloader for the Mico32 DSP ECP2 board - JTAG flasher tool based on openwince...
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16 years ago
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Ph.D in France
Hi friends, I am working in the field of microelectronics particulary int the field FPGA's/mircontroller based products. I want to persue my Ph.D in France. But I don't have any information about...
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16 years ago
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Regional Clock Resources
Hi, I am having some trouble with implementing several serial links per IO Bank in Virtex5. An IO bank is about the same size as a clock region. Each clock region has 4 BUFIO and 2 BUFR available. I...
1
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16 years ago
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New Xilinx forum.
Hey Guys, Did any of you get an email like this last weekend(see below)? What a crock! Like a mug, I signed in tonight with my regular Xilinx login, to check it out. Not exactly popular yet... I'm...
39
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16 years ago
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39 | |
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Microblaze GPIO interrupt
I've hit a brick wall with this. I just can't figure out what I'm doing wrong, or not doing right! I just want to generate an interrupt when the pushbutton (PB) is pressed. This is the only interrupt...
1
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16 years ago
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EDK 8.1
All, We are desperately in need of EDK 8.1 for programming Xilinx Virtex-II MK325 . The disk we had is lost. Xilinx and its distributors NuHorizon o Avnet do not stock or sell 8.1 anymore sinc 9.1 has...
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16 years ago
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TEMAC Performance Issues with Virtex 4FX
Hello. I have designed a small application on a Virtex4FX based on the Xilinx lwIP Echo Server example ( ). I haven`t done any dramatic changes to the example, in general terms I modified the socket.c...
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16 years ago
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Digilent USB module linux
Hello, I try to communicate with a Digilent S3- Board via USB-Module 2 using linux (libusb). Has anybody successfully transmitted or received data this way (the win32 way works) ? best regards Andreas
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16 years ago
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FPGA board connected to CMOS chip: ESD hazards?
I need to connect the Xilinx ML402 board to the 3.3V CMOS chip. I am concerned about the ESD that could burn the CMOS chip. I am concerned about the possibility of the ESD when CMOS is being connected...
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16 years ago
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AREA_GROUP Map Error
I have a design that instantiates four copies of a module and I am using Xilinx's AREA_GROUP constraint to partition each instantiation into its own 1/8th sector of the FPGA. I ran across a few...
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16 years ago
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Problem about clock switch in Quartus II 6.0
I use Cyclone II to implement image processing. There are a CMOS image sensor, a FPGA chip, and a SRAM on my board. I meet a new problem when I try to optimize my design. In my old instance, I use the...
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16 years ago
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