Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Webpack 9.1 and Samba
I just upgraded? my computer (was W2K) and ISE6.3 to Windows XP and Webpack 9.1 And now have problems with project/working filea mounted on a Samba server (3.0.10) This same setup worked fine with...
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16 years ago
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embedded tips
Hi all, I've been targeting the general logic of Virtex-2s and Virtex-4s for years now, but I'd like to start getting into embedded stuff... specifically programming the embedded Power PCs or the...
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16 years ago
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Xilinx Xilfatfs SystemACE library and partition format
Hi, I have been struggling on a Virtex II Pro in order to make the XilFatFS work properly. What I want to do is use the Compact Flash to boot the board which I did successfully by formating the CF...
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16 years ago
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Amount of wire and logic
Dear Since Xilinx does not report wire utilization and technology data, I expect that Given FPGA device family : (1) There is a constant ratio of INTERCONNECT to LOGIC. (2) When amount of LOGIC...
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16 years ago
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DDR/DDR2 controller - core
Hi I want to use in my project (with Spartan3 or Cyclone2) a DDR/DDR2 DIMM module. I have chosen DDR because is avaiable and cheaper than SDR. I have no experience with memory controllers and not to...
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16 years ago
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I2C master connected and tested with LEON Processor
This design uses the open core's I2C master. The core's CPU interface is modified from WISHBONE to AMBA/APB. The latter is done in order to test the core and its new APB interface with LEON processor....
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16 years ago
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EDK (XPS) - Path problem causing "Generate Libraries and BSPs" to fail...
Hi, I'm using EDK/XPS 9.1.02J on Windows XP. I'm working my way through a through the document tutorial "EDK Concepts, Tools, and Techniques". I seem to have come to a problem when attempting to...
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16 years ago
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EDK speed issue
Every time I make a minor change to one of my local pcores I have to do a "Clean Netlist" to ensure that the change is carried out. I find this very painful since it then rebuilds all the other IPs....
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16 years ago
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SystemACE, xilfatfs and feof()
Hi all, I'm doing a project with a Xilinx University Project Virtex-II Pro board. For this I'm using the compact flash card-reader interfaced with a microblaze instantiated on the FPGA. I'm using EDK...
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16 years ago
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Reset and DCM
Hello all, I'm working on a FPGA design that runs in board with a Virtex-II that doesn't have any reset signal. I have some doubts about this. On one side, It is supposed that everthing in the FPGA is...
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16 years ago
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spartan3 picoblaze how to make .bmm file work
I'm a newbie in fpga design, and am really struggling to create a bmm file that works. I am using an Spartan-3A starter kit, with ISE 9.2.0i on Linux. I am working with the dna reader project, and am...
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16 years ago
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secure interfacing between an fpga and a connected device
I have - MY_FPGA DEVICE I want to make it so that the DEVICE operates only if MY_FPGA is connected to it. I need to make this connection secure enough to pass Military Export controls. Any ideas? I am...
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16 years ago
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Xilinx Webpack 9.1: How do I export a netlist to another project?
I've searched Xilnx's website and documentation for help on creating your own IP-cores (for distribution to third-parties) -- but I didn't find anything. So I'm asking here.... I want to develop an...
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16 years ago
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what the AC exactly short for here...
hi, I can't find the exact mean of AC in this phrase "AC-non-redundant fault" that refered in following abstract: can anyone tell me... AC means: alternative current, or Automatic Check, or Access...
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16 years ago
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High Speed ADC
Hi all: I am trying to reconstruct a periodic exponential signal curve. The signal is in the order of 10-20mV. The total length of this curve is 100ns. Even though the total length is 100ns, the peak...
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16 years ago
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