Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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about mb-gcc error???
what's wrong with following error???? [root@184pc140 bin]# ./mb-gcc hello.c /home/devel/uclinux/bin/mb_tools/bin/../lib/gcc/microblaze/ 3.4.1/../../../../microblaze/lib/libc.a(write.o): In function...
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16 years ago
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DDR2 @ 400 MHz and Xilinx Spartan-3A[N] kits
Xilinx has three very similar kits: - Spartan-3A Starter Kit, - Spartan-3AN Starter Kit, and - Spartan-3A DDR2 SDRAM Interface Development Kit. Only the latter is promoted as supporting DDR2 @ 400...
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16 years ago
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Mico32 bootloader
Evnin' Not final but a small step before Lattice is ready with their Linux (o; cheers rick
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16 years ago
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Virtex 4 IBUFG to DCM routing question
Hi all, Question on the clock routing in a Virtex 4 LX 25 that I haven't found the answer to today. I have an input clock, single ended, on a clock pin in the top half of the centre slice of the die....
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16 years ago
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ChipHit: ASIC, FPGA, EDA Search Engine
Hi, I recently created a Google custom search engine called ChipHit at Please take a look and provide suggestions. I spend many hours a day searching the internet for ASIC, FPGA, and EDA tool topics...
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16 years ago
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Multiplication Problem on Microblaze Software
Hi, I want to do multiplication operation in my Microblaze's Test_Applicatio in Xilinx Plaform Studio. But i get some you help me? This my code temp1=j=16; temp2=temp1*0.5;//error occurs when i use "...
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16 years ago
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Xilinx PACKER warning bout carry
What does this "PACKER" warning mean? Lut _ driving carry _ can not be packed with the carry due to conflict with the common signal requirement between Lut inputs and the Carry DI/MAND pins. This...
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16 years ago
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System ACE failure on ML405
I keep running into a System ACE problem on the ML405 when trying to get my own ACE file to load. - I've properly formatted the CF card (as described in Answer Records #14456), and I've verified this...
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16 years ago
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How to save simulation results in Xilinx ISE ?
Hi everyone, I am using Xilinx ISE simulator for behavioral simulation of a large circuit. I would like to save simulated results, to avoid running the simulation again, which takes quite some time....
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16 years ago
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Xilinx DDR2 SDRAM controller performance
I am using the MIG generated DDR2 controller in a V5 device. The DDR2 runs at 266 MHz. I am meeting timing, but I am finding the performance of the controller to be a little dissapointing. When I am...
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16 years ago
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Delaying a pulse train
I have to delay a pulse train by a given number of clocks on the same domain as the pulse to be delayed. The best approach I can think of is to run a counter of sufficient width and log pulse...
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16 years ago
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SDRAM Controller
Hi I have designed an SDRAM controller and nearly ready to synth and P&R. M question is do I need to add any offset constraints to the ucf? I see tha the Xilinx XAPP134 uses them but the newer DDR...
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16 years ago
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Xilinx Spartan FPGA : Strange Errors
Hi, I wonder if anyone has seen something like this. I have an FPGA design targeted at an Spartan xc3s1500 and using ISE8.2. We are using a spartan evaluation board with some 7 segment LED's. If I...
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16 years ago
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Virtex4+PPC+ext. RAM: Problems generating ACE files (solved!?)
Hi *, [Warning: Long post, includes patch for I am working with a custom Virtex-4 based board design using an internal PowerPC core and external SDRAM for code and data. Using the standard EDK flow,...
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16 years ago
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xst fails...
Hi, I'm currently trying to synthesize a big design on a Virtex4-VLX100. Now the problem is, that xst fails and just gives the following line: Process "Synthesize" failed Is there a way to hunt for...
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16 years ago
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