Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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help to sort out the errors
hi i have wrote the program for nios processor. when i am trying to complie it, i am getting the follwing errors. can anyone help me out in rectificing the errors **** Build of configuration Debug for...
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16 years ago
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Call for Papers: RAAW-2
================================================================ We apologize if you receive multiple copies of this CFP ================================================================ SECOND ANNUAL...
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16 years ago
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MicroBlaze and ChipScope
Hi, I want use ChipScope with MicroBlaze but I can't find tutorial or etc. I use EDK 8.1 and ChipScope 8.1. Any body has a source about it or link? Thanks
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16 years ago
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System Generator Question: Flopping the inputs and outputs
Hi, I'm trying to implement some control circuits in Mcode. I want to have the inputs and the outputs of the circuits to be flopped. I'm having trouble finding guidance in the documentation as to how...
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16 years ago
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Spartan-3A DSP vs. Cyclone III Power-wise
Hi, Well the subject says it all. Just wondering how does Spartan-3A DSP compares to Cyclone III in terms of power efficiency. I know the spartan is 90nm and hence should be less favourable. However,...
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16 years ago
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help on how to assign data to the function of nios program
hi. i am a newibe to nios processor. i have a written a program in nios IDE. i am taking the inputr data from the pio core of the DE borad, from the external interface. now how can i send that data to...
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16 years ago
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FPL 2007 : Final call for participation
We are pleased to invite you to participate in the 2007 Field Programmable Logic Conference which will be held in Amsterdam, the Netherlands from August 27 until August 29. FPL is the oldest and one...
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16 years ago
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Old issues of XCell magazine
Somebody asked for access to old XCell magazines. I was able to download all issues #17 through #39 ( 2Q1995 through 1Q2001) by clicking on: ftp:// etc. Peter Alfke
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16 years ago
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At what frequencies is it acceptable to generate a clock from a register?
How would one best judge when it is acceptable to generate a clock from the outputs of an internal register instead of using the standard blocks such as DCM's? My design will go onto an XC2V8000-5...
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16 years ago
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exe file in modelsim
Hi all, Can anyone suggest me how to run an exe file in modelsim...I have tried using sccom -g basedes.cpp baseDesc.cpp and linking was successful but i dont know the command to run an exe file Thanks...
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16 years ago
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Multiple MicroBlazes error
Hi all, I am currently work on multiple Microblazes too. I met this error message when instantiion....
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16 years ago
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Voltage translation question
I need to do the voltage translation from V5 3.3V push-pull output to one of the traget device input. The input accepts 0.8V on the positive rail and -2.5V on the negative rail. I am looking at a pair...
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16 years ago
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GPIO_performance
Has any one measured the cycles needed for a single I/O function using a GPIO peripheral with the PowerPC processor (Virtex-II Pro device). I have measured using a counter and i takes 115 cycles. I...
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16 years ago
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MCS -> BIT
Hello I have just the MCS file and I want to configure directly my FPGa with a bitstream. So I had to convert the MCS in BIT. What I have done: 1)MCS->HEX with promgen: promgen -r -p hex 2)HEX->BIT...
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16 years ago
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Globally Asynchronous in FPGA
Hello Let me ask one question. design, because (1) There are enough registers, (2) There are fat clock trees for entire chip, (3) There are IPs for different clock synchronization management (for...
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16 years ago
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