Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
New keyword 'orif' and its implications
Hi, I open a new topics from previous one to try to stir another round to introduce a new keyword 'orif'. Hi Andy, A group of signals is defined as mutually exclusive if either no signal or only one...
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PLL Power and m/n ratio
Hi Folks, I am wondering the implications on PLL power compared to the m/n ratio that is used to generate a particular frequency. So which consumes more power? a. 25MHz src clock into the PLL that...
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6
 
Re: ANNC: FPGA Noise Fundamentals Webcast
Is there a text version? I've never understood the logic of listening to someone drone on in a thick foreign accent when the same person could just publish the text or write a web article that we can...
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tricking bitgen into creating rom-like behavior
Is there a way I can read in a text / ascii /binary file AFTER P&R is done to mimic a ROM ? I could use block-RAM instead of ROM to read in this file. The normal way to do this is would be to read in...
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Null statement in VHDL
Hi, I rarely use null statement in my designs. I check the definition of null statement from book "HDL Chip Design" written by Douglas J. Smith. It says that "Performs no action. Has no other effect...
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bidirectional pin help
Hi everyone I am working on some FPGA project and I need to define one port as bidirectional. This is my VHDL code...
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15
 
Looking for VME-Bus Core
Hello, does anybody know a synthesizable VME-Bus Core. A few years ago there was a core outside there from silicore with wishbone interface. Is anything similar out there? Regards Christian
 
Partial reconfiguration using ICAP
HI all, I am trying to download Partial bit streams created by Planahead , through ICAP Xilinx board i am using is XUP (xc 2vp 30). I download bitstreams into DDR ,then i am trying to transfer the...
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Newbie with ISE 9_2_02i_lin gets error : Process "Translate" failed
Downloaded ISE 9.2i day before yesterday. Installed t9_2_02i_lin update and am just going through the counter example in the "ISE 9.1i Quick Start Tutorial" that is in...
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[xilinx ise simulation] how to keep all settings between runs
Hi all Is there a way to keep the settings (specifically the format of signals, and the widht of the name and value column) between runs of the simulator? I find it quite tedious to keep selecting...
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Overriding a VHDL generic for command-line driven synthesis with ISE
Hi friends i have a question regarding ISE Webpack (7.1 to 9.1 versions): Is it possible to override the value of a VHDL generic (e.g. for the top-level module under synthesis)??? Does there exist...
 
A beginner asks questions about synthesis under Xilinx XST
I've realised there are many things I don't know about the synthesis process under Xilinx XST. The top level of code is associated with a .ucf file, which defines pinout and timing constraints....
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2
 
Implementing MIPS Memory Hiarchy
Hi there, I have a more general question about processor design, hope that is alright ;) I am just implementing some kind of MIPS core, and I am about to integrate the memory hiarchy with instruction...
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3
 
hwicap for EDK 9.1
Hey guys & gals, I've been experiencing some difficulty using the opb_hwicap for EDK 9.1. I'm trying to use it for reading/writing BRAM data w/ it's new 32-bit, virtex4 support. Anyway, I cannot seem...
 
Dynamic power estimation using Xpower
Hi. I am using Xpower for estimating the total dynamic power consumption of my processor which is described in VHDL. I would be thankful if you could tell me how I can calculate this value using the...
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