Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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V5 Configuration via SPI
Hi *, on one of our next boards, I'd like to use the Virtex5 feature to have it program itself from an external SPI flash. In that case, the FPGA will provide the SPI clock via the dedicated CCLK pin....
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16 years ago
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flip-flop enable
Hi everyone, I'm experiencing something weird in my code implementation that leaded me to question which is the correct way to enable a flip-flop. Assuming I have a clocked output of a FF one cycle...
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16 years ago
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Interesting FPGA/JTAG project.
Guys, I saw this on Slashdot. Interesting article about a guy who used some rescued FPGA boards to do some number crunching. Also, there's a cool JTAG tool. Cheers, Syms.
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16 years ago
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How to add additional FSL interface to customized IP?
Hi, I would like to create a system like below: uBlaze customized IP uBlaze Could anyone tell me whether it is possible to do that? Is there any constraint about the number of FSL pairs each...
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16 years ago
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Chip Designing made Easy
Chip Designing Made easy To Understand the "World of Miniaturization" and Appreciate the "Art of Chip Design" a senior citizen in the field of Chip Design Industy Shares his Design Expertise. Explains...
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16 years ago
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BlockRAM connection error
Hi all, I met a wired BlockRam connection error when I tried to build a mutilple processors system using EDK. Hope anyone can give me some hint. Here is the background. With the EDK, we can create a...
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16 years ago
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what does asynchronous loop mean?
Is it bad to have async loop? If so, why?
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16 years ago
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Xilinx ML40x Mouse VHDL Wanted
Does anybody have VHDL code to run the mouse port on an ML40x dev board? Brad Smallridge Ai Vision
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16 years ago
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signal termination in spartan 3e starter kit
hi i am new to FPGA designs. i have a question about signal termination. the spartan 3e starter kit has a 10 ohm resistance in series and 10 pf capacitor to ground between CCLK pin of FPGA and CLK pin...
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16 years ago
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Simple Project involving microblaze
Hello Everyone! Can anyone suggest a simple exemplary FPGA project involving microblaze using ISE tools rather than EDK? I am pretty at ease with desiging custom IP modules targetting Xilinx FPGAs,...
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16 years ago
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Memory bandwidth of the 3A kit
Antti, did you ever get a feel for what memory bandwidth you actually get with this setup ? For example, if you had a blockram being constantly filled from DDR2 ram, how many MB/sec you can actually...
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16 years ago
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Wifi with a Virtex 4
Dear all, I'm just starting to look into the possibility of adding 802.11g to one of our products which is based on a Virtex 4 FX. Does anyone have any experience with this? Is there 802.11g MAC IP...
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16 years ago
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Is it possible to make bit files generated by Xilinx ISE readable?
I thought the bit files generated by Xilinx ISE should be in plain binary format, but actually the .bit file is unreadable when opened in XEmacs, just wondering whether it is possible to make these...
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16 years ago
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Xilinx blockram FIFO async reset annoys me (and Modelsim)
Hi all, I'm facing a problem with Xilinx Coregen blockram fifo. At some point I want to reset it with a signal generated in a state machine. The reset makes the internal pointers in the FIFO to point...
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16 years ago
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Spartan 3E - Readback via JTAG
Hi, i'd like to readback all the contents of an XC3S500E via the JTAG interface. Because this option is not implemented in the iMPACT-tool (well, it is implemented via the verify-option, but the...
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16 years ago
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