Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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ANNC: New Boundary-Scan Software
Dear All, Please have a look at Scanseer ( a new software for 'manual' boundary-scan testing. Scanseer does not generate SVF tests, but it allows to: * monitor pins with no interference to normal...
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16 years ago
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Problem locking a DCM driven by FX output of another DCM
I have a design with 3 DCMs. The first DCM generates 280 MHz out of 210 MHz. It is then divided by 2 and 4 in a PMCD. There are 2 more DCMs, one driven by resulting 70 MHz clock and another by 140 MHz...
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16 years ago
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Clock boundary crossing
What are the different ways of crossing clock boundaries. Is there any website with good information on that. Thanks Amish
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16 years ago
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Free downloadable PDF graph paper.
Dear All, I found this online and found it useful. Maybe you will too. Syms.
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16 years ago
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Is it possible to perform gate level simulation on a design without a reset?
Hi, If an Altera design does not have a reset, then what happens to the registers during gate level simulation? I assume that the Q outputs are initilaised to 0, but what happens with the D inputs, I...
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16 years ago
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load/read/ commands assembly PowerPC. Help Needed!
Hello all, I am trying to load a 32bit data (word) from the PortB of a BRAM to a GPR (general purpose register) of the PowerPC. Address Map for Processor ppc405_0 (0b0000010000-0b0000010011) ppc405_0...
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16 years ago
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Question about timing of Xilinx Core generated counter
Hi, I find a problem in the simulation of watchvhd example from Xilinx ISE 8.2 or 9.1. There is a Core generated counter, named xcounter. Even I perform behavioral simulation, its 4-bit output (q) has...
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16 years ago
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JTAG CPLD Configuration
Hello I have a Xilinx XCR3064 CPLD with its JTAG pins hooked up to some digital I/O pins on a uC. I intend to configure the CPLD from a binary file held in uC flash by bit-banging the uC pins. So far...
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16 years ago
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REGARDING ILA in FPGA EDITOR
Hi all, I am using ISE 9.1I and Chipscope 9.1i. I tried to change some nets in ILA thorogh FPGA EDITOR ila command. It allowed me to change through Change Net Option. I generate Bit file with the...
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16 years ago
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FATAL ERROR ISE9.1i
Hi, i get this message when i run post & route: Starting Placer FATAL_ERROR:Portability:PortDynamicLib.c:358:1.27 - dll open of library failed due to an unknown reason. Process will terminate. Process...
2
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16 years ago
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¡¾Nios II¡¿How Can I Find Out These Functions £¿
I'm a beginner in the Nios II System. When I learn the examples provided by Nios II IDE, I always see this type's function : IOWR_ALTERA_AVALON_PIO_DATA(LED_PIO_BASE, count); The function appears in...
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16 years ago
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How to deal with the tempary coefficient in the FPGA design
In my FPGA design, I need a result of EXP(z: is complex) as a tempary coefficient for other calculations. I've known to deal with the real part and imagin part separately. But I don't know how to deal...
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16 years ago
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high bandwitch ethernet communication
Hello, In our application we have to receive and merge several proprietary serial channels (200 MHz) over fibers, and send all the data over Gigabit Ethernet. The bandwidth is ~60 MByte/s, sustained....
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16 years ago
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clock skew problems
Hi all, I've got a FPGA design with a lot of clocks! I know this is not really good, but I've to implement a microprocessor initially designed for an ASIC. The microprocessor uses combinatorial...
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16 years ago
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EDK9.1 linux registration fails (vista ok)
Hi groups, is there any reason for edk 9.1 registration failure with linux (I use the same id that successfully register edk on the same dual boot vista/ ubuntu laptop ?)
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16 years ago
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