Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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VHDL Synthesis Error
Hello all, I am trying to implement a network adapter that sends small packets to and from FPGA boards using VHDL. I want to download this and test it out, but I am getting the following synthesis...
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16 years ago
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LVDS pin placing on CYCLON II problem
Hi, I'm working on design with LVDS signals and when I'm trying to place LVDS inputs at dedicated pins I got : Error: Non-differential I/O pin addr[8] in pin location 86 and pad 103 too close to...
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16 years ago
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Quick question for an Altera wizard
I have a verilog design on Spartan 3 which needs to move to Cyclone II. The design has 7 128x1 bit asynchronous ROMs using ROM128X1 primitives (this is called distributed ROM?). Does Cyclone II have...
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16 years ago
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Minimize power consumption
Hi. I have a question. I have a special y=f(x) function. It takes 32 bit at input and it have something at output. Function is unrolled, it computes result alsmost "immediately", and it doesn't...
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16 years ago
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Anyway to stop Altera Stratix II SignalTap data acquisition
I set the SignalTap memory depth to 16K and would like to collect exactly that many data points after the trigger. However, it seems SignalTap will only stop collecting (and therefore overwriting the...
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16 years ago
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Help getting sdram running with EDK.
I've been struggling for weeks to get sdram to work correctly on a newly designed board. I was hoping that someone might have some suggestions to help me out with my struggle here. This is what I am...
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16 years ago
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Nios II -- Why does this error occur ?
When I Run the NiosII project, there is sometimes this error info. in the console: nios2-terminal: exiting due to ^D on remote But Why? it is relative with the pointer ? Thank you very much!
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16 years ago
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New keyword 'OIF' and its implications
Hi, 1. Based on the previous very benefitial discussions and my observation on the topics, I decide to recant the following claim: Whatever assertion onehot0() can do, 'orif' can do better. 2. In...
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16 years ago
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RE: FPGA/VHDL digital Design permanent role - Oxford
Hi, I have a really exciting R&D role with a Media/Broadcast organisation in the Oxford area. If you have a solid background of VHDL digital design knowledge and fancy a move into a busy and exciting...
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16 years ago
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SRAM on Cyclone Devices
Target Device: CYCLONE My project allocates some RAM and initializes it by an Intel Hex File. The Simulator correctly shows the initialized data. lpm_ram_dq ram ( .address (_addr), .q (_dout), .data...
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16 years ago
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How to simple convert a hex or mif file from Altera to Xilinx coe file?
Hi, How to simple convert a hex or mif file from Altera to Xilinx coe file? Do you know any little software? Regards Bernard Esteban MAF Agrobotic
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16 years ago
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[Nios II] How does the PIO Core generate a interrupt?
I have designed a counter, it works like this: when the counter reach a number , one of its output pins generate a high level signal, this pin connects with the SOPC module. How can I achieve this...
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16 years ago
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Rocket IO clock
Hi there, I'm not very pleased reading the virtex 5 datasheet dealing with Rocket IO transcievers. In fact the Xilinx datasheets are not comprehensive and dificult to read. Every transciever bank has...
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16 years ago
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DDR Simulation via MIG
I am looking into a MIG-generated DDR SDRAM interface and am having trouble with the simulation. I can see the interface go through the intialization sequence, but when it gets to the first dummy read...
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16 years ago
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VCCAUX too high on a Spartan 3 design
Using linear adjustable regulators for VCCINT (1.25v), VCCIO (3.3v), and VCCAUX (2.5v). VCCINT and VCCIO are dead on, but VCCAUX is 2.72v, 2.88v, and 2.92v on the 3 boards I grabbed and measured. All...
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16 years ago
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