Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Address sensitive process, Xilinx virtex2pro
hi, i'm trying to write a process that is sensitive to a given address, i wrote something like this: my_proc: process (Bus2ip_Clk) begin if (Bus2ip_Addr = X"some address") then Bus2ip_Data
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16 years ago
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FPGA Archives
How do you get messages from archives? Google brings up headings that I may want to read, however, when I click on those headings I go to the archives that are listed by year and month. There isn't a...
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16 years ago
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Good VHDL reference?
It seems I have misplaced my VHDL book a long time ago and I can't figure out where I left it. In short: I need a new VHDL book :-( Can anyone recommend a good generic VHDL reference? I'm not looking...
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16 years ago
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PCI byte enalbes in read cycles
Hi all, I'm implementing a PCI interface in FPGA, but I'm stuck trying to figuring out what happens with byte enables in burst read cycles. Specifications are not clear about this point, saying that...
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16 years ago
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Stratix III Memory usage efficiency
Has anyone else encountered the problem of shape and size of M9K blocks (I suppose this applies to other devices also). e.g. if I want a 2720X18 memory (48960 bits), the wizard will construct one out...
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16 years ago
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application about hardeware attributes
Hi everyone, I'm a student of the RWTH (or university of) Aachen, Germany. Right now I'm writing my diploma thesis at the Chair of Computer Science "Software for Embedded Systems". With this thesis...
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16 years ago
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microblaze toolchain compilation question
hello all, I'm trying to compile the microblaze-toolchain from source on a 64 bits linux system, but got stuck. The source from the petalogix repository doesn't compile. a first problem was solved...
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16 years ago
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hydraxc
hi i have a question. is there a xbd file (for edk) for the hydraxc available? and where can i find some documentation besides the hydraxc web page. (because there is not much on there). perhaps some...
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16 years ago
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Xilinx core generator MIG module generates a slow timing for a DDR2 SDRAM controller
Hello. I've used the Xilinx core generator MIG module to generate a DDR2 SDRAM controller. The design supports generics for the ram timings. E.g. 15000 ps for the precharge-command delay (tRP). When I...
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16 years ago
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ACM SAC 08: DEADLINE EXTENSION (16 Sept, 2007)
SUBMISSION DEADLINE: September 16th, 2007 SUBMISSION SITE: CALL FOR PAPERS - SAC 2008 The 23rd ACM Symposium on Applied Computing March 16 - 20, 2008, Fortaleza, Cear=E1, Brazil by University of...
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16 years ago
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Uses of Gray code in digital design
Hello, Most books on digital design discuss Gray codes. However, most of the focus is on generating these codes, rather than detailing their uses. I read the Wikipedia article: it doesn't provide...
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16 years ago
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Question about Virtex-4 DCM
I have an application where I need to model a circuit that has two power rails. A Vitrex-4 has only one internal power rail, so I was thinking about disabling the DCM to simulate a power-down. This...
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16 years ago
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1/2 Convolutional Encoding of CNAV Data
Does anyone know how to implement a 1/2 (1 binary bit in, 2 out, message length of 7) convolutional encoder in HDL? I am trying to implement the encoding of CNAV data and am unclear of where the tap...
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16 years ago
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What is called carry chain structure in FPGA is called in IC?
Hi, I want to know what is called carry chain structure in FPGA is called in IC? Thank you. Weng
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16 years ago
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What is the name of Altera latest and most advanced chip serial that is competable in technology with Vertex V in terms of system strucute(LUT6...)
Hi, I would like to know what is the name of Altera latest and most advanced chip serial that is competable in technology with Xilinx Vertex V in terms of system strucute(LUT6..., not 65nm). Thank...
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16 years ago
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