200MHz ucf constraints for Xilinx DA Decimation by 2

Hi folks,

I have generated a DA filter in coregen with the following specs:

Decimation by 2

40 taps symmetric 18 bit coes (signed) 12 bit input 2 clock cycles per output

The input rate is 100MHz down to 50MHz.

However, I want to clock it at 200MHz down to 100MHz to save area - hence the 2 clocks per output.

I am targetting an xc2v3000fg676-5 and I am pretty sure this is achievable since the polyphases need only run at 100MHz - only the data demuxing needs to run at 200MHz.

Constraining the whole lot via the CLK signal to 5ns (200MHz) doesn't work - gets to about 177MHz with 16 logic levels across what is clearly a carry chain (which needs only to run at 100MHz).

Here is what I tried in the ucf to try and tell ISE 5.2.03i what to do:

NET "CLK*" TNM_NET = "CLK"; TIMESPEC "TS_CLK" = PERIOD "CLK" 5 ns HIGH 50 %; NET "ND*" TNM_NET = "ND"; TIMESPEC "TS_CLK_ND" = FROM "CLK" TO "ND" "TS_CLK" * 2;

This doesn't work though - the timing report still moans about a carry chain failing the 5ns constraint even though it would meet the 10ns constraint it should be tied to. I think the logic will work at these rates but it would be nice to know for sure via correct contraints.

So, can someone suggest some ucf details I can use to tell the tools what to do please? Do I need to specify some internal signal rather than ND?

Thaks for your time,

Ken

--
To reply by email, please remove the _MENOWANTSPAM from my email address.
Reply to
Ken
Loading thread data ...

Hi Ken,

needs

work -

chain

it

would

to

What you've described is known as a multi-cycle path (data updates only every X clock cycles allowing for the operation to span multiple clock cycles). I don't remember the exact ucf syntax, but I think it's a generic device to device constraint (the example in the Xilinx documentation is very good). Please note that you may specify this time as "X * ", which allows your design to be easily scaled for different frequencies.

Hope this helps, Alvin.

Reply to
Alvin Andries

hence

achievable

what

address.

to

Thanks for the response Alvin.

I am aware that I am trying to specify a multicycle path - I have used the syntax I posted above (which does have an X * BTW) in other similar situations and successfully specified a multicycle path - that was for VHDL that I wrote however and not for an edif generated by coregen.

Cheers,

Ken

Reply to
Ken

Hi Ken, When I was working on a part of my project that had a clk and a clk2x, I didn't even need to specify the 2x period, as my signal was comming from the DCM, and ISE found that one itself. However, I did need to insert a timing ignore constraint (TIG) on the path that crossed my clock domain boundary. I'm always queasy about doing such things, and I haven't tested it out physically yet, so take it for what it's worth, but it got rid of my error messages, at least. Pierre-Olivier

Reply to
PO Laprise

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.