Hi folks,
I have generated a DA filter in coregen with the following specs:
Decimation by 2
40 taps symmetric 18 bit coes (signed) 12 bit input 2 clock cycles per outputThe input rate is 100MHz down to 50MHz.
However, I want to clock it at 200MHz down to 100MHz to save area - hence the 2 clocks per output.
I am targetting an xc2v3000fg676-5 and I am pretty sure this is achievable since the polyphases need only run at 100MHz - only the data demuxing needs to run at 200MHz.
Constraining the whole lot via the CLK signal to 5ns (200MHz) doesn't work - gets to about 177MHz with 16 logic levels across what is clearly a carry chain (which needs only to run at 100MHz).
Here is what I tried in the ucf to try and tell ISE 5.2.03i what to do:
NET "CLK*" TNM_NET = "CLK"; TIMESPEC "TS_CLK" = PERIOD "CLK" 5 ns HIGH 50 %; NET "ND*" TNM_NET = "ND"; TIMESPEC "TS_CLK_ND" = FROM "CLK" TO "ND" "TS_CLK" * 2;
This doesn't work though - the timing report still moans about a carry chain failing the 5ns constraint even though it would meet the 10ns constraint it should be tied to. I think the logic will work at these rates but it would be nice to know for sure via correct contraints.
So, can someone suggest some ucf details I can use to tell the tools what to do please? Do I need to specify some internal signal rather than ND?
Thaks for your time,
Ken