I have 2 clock inputs coming into the FPGA through a clock-capable IO pair (AN19 and AN20). The clock inputs are of the same frequency, but not in phase. Is it possible to route each through their own IODELAYs, and BUFIOs, to separate local clock nets? I want one clock going to a bunch of ISERDES "CLK" ports and the other clock going to the same ISERDES "CLKB" ports.
Here's some of my code:
cq_IDELAY_INST: IDELAY generic map ( IOBDELAY_TYPE => "VARIABLE" ) port map ( I => cq, O => cq_delayed, C => MemClk, CE => IDELAY_En(0), INC => IDELAY_Inc, RST => IDELAY_Rst(0) ); cq_BUFIO_INST: BUFIO port map ( I => cq_delayed, O => dq_rd_clk );
cq_l_IDELAY_INST: IDELAY generic map ( IOBDELAY_TYPE => "VARIABLE" ) port map ( I => cq_l, O => cq_l_delayed, C => MemClk, CE => IDELAY_En(1), INC => IDELAY_Inc, RST => IDELAY_Rst(1) ); cq_l_BUFIO_INST: BUFIO port map ( I => cq_l_delayed, O => dq_rd_clk_l );
IO_DQ: for i in 0 to 17 generate
dq_in_ISERDES_INST : ISERDES_NODELAY generic map( BITSLIP_ENABLE => FALSE, DATA_RATE => "DDR", DATA_WIDTH => 4, INIT_Q1 => '0', INIT_Q2 => '0', INIT_Q3 => '0', INIT_Q4 => '0', INTERFACE_TYPE => "MEMORY", NUM_CE => 2, SERDES_MODE => "MASTER") port map ( BITSLIP => '0', CE1 => '1', CE2 => '1', CLK => dq_rd_clk, CLKB => dq_rd_clk_l, CLKDIV => MemClk, D => dq_in(i), OCLK => MemClk, RST => rst, SHIFTIN1 => '0', SHIFTIN2 => '0', Q1 => i_dq_in_falling(i), -- falling edge data Q2 => i_dq_in_rising(i), -- rising edge data SHIFTOUT1 =>open, SHIFTOUT2 =>open); end generate;
ISE is giving the following error in the MAP phase:
Running timing-driven packing...
Phase 1.1 ERROR:Place:730 - The I/O clock buffer (BUFIO) "sr0/cq_l_BUFIO_INST" is driven by IODELAY component "sr0/cq_l_IDELAY_INST/IODELAY". The IODELAY component must be placed into a clock capable I/O tile and the BUFIO component must be placed into the corresponding BUFIO site. The following issue has been detected: All of the logic associated with this structure is locked and the relative placement of the logic violates the structure. The problem was found between the relative placement of IODELAY sr0/cq_l_IDELAY_INST/IODELAY at site IODELAY_X1Y100 and BUFIO sr0/cq_l_BUFIO_INST at site BUFIO_X1Y11.
I've LOCated my IODELAYs and BUFIOs to those components next to the pads:
INST "sr0/cq_IDELAY_INST/IODELAY" LOC = "IODELAY_X1Y101" ; INST "sr0/cq_BUFIO_INST" LOC = "BUFIO_X1Y10" ; INST "sr0/cq_l_IDELAY_INST/IODELAY" LOC = "IODELAY_X1Y100" ; INST "sr0/cq_l_BUFIO_INST" LOC = "BUFIO_X1Y11" ; NET "sr0_cq_l" LOC = "AN19" ; NET "sr0_cq" LOC = "AN20" ;
Does anyone have any suggestions? I read in the Virtex-5 User Guide that there are 4 clock nets per IO column. I'm wondering if perhaps my 2 BUFIO signals cannot be used at the same time, or if they can't drive different local clock nets.