Hi
I should have some kind of PRNG that generates me for each clock
2 random bits. I was thinking for a start of implementing an 8-bit LSFR and just using then the last two bits as output. I am just wondering if there is an easy way to change the seed in each run when I initialise the temp variable? The design should work on an FPGA in the end ;)library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
entity PRNG is port ( clk : in std_logic; R0 : out std_logic; R1 : out std_logic ); end PRNG;
architecture Behavior of PRNG is
begin
process(clk) variable temp : std_logic_vector(7 downto 0) := B"01111101"; begin temp := (temp(1) xor temp(0)) & temp(7 downto 1); R0