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1D or 2D Placement for dynamically partially reconfigurable architecture

Hi All:

There are many papers about the 1D or 2D placement. However, the papers are almost for the algorithm discussion. The current method for dynamically partially reconfigurable architectures is EAPR flow, but the DPR blocks need to be defined at design-time by using the ucf file. All the area constraints are finally included in the static_full and partial bitstreams. So, I am very confused how 1D and 2D placement can be applied to a =93real=94 DPR system at run-time. Are there any research groups who can apply such placement methods in a =93real=94 DPR architecture? I know that some proposed methods, which contained a specific filter to re-modify the location information in the bitstream, can relocate a partial bitstream to a new location. However, the area sizes of DPR blocks need to be the same. However, for example, two DPR blocks are implemented at design-time. Is it possible that the two DPR areas can be merged for placing a partial bitstream that needs both the resources of two DPR blocks like real 1D or 2D placement at run-time? Is there any architecture that can freely be placed the partial bitstreams at run-time? Thanks very much!

Best regards, Huang

Reply to
grant0920
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I suggest you read this paper from FPL 2007:

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The authors developed tools to dynamically relocate partial bitstreams in Xilinx devices, along with a channel router to wire them up again. This does enable the use of module placement algorithms in real-time and frees the design from fixed module size constraints.

Stephen

Reply to
stephen.craven

Hi Huang,

if you like, you can have a look at the following papers from FPL 2007 and ERSA 2007:

"A Design Methodology for Communication Infrastructures on partially reconfigurable FPGAs", presented at FPL 2007, shows a design flow, which allows to place several hardware modules within a partial reconfiguration region. Thus, the resources can be used more efficient than compared to other approaches. "Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs", presented at ERSA 2007, can be seen as an addition to the FPL-Paper. An "embedded communication macro" is introduced which enables the communication between the modules.

The methods can be used for 1D as well as 2D placement.

Best Regrads,

Jens

Reply to
Jens Hagemeyer

Thanks very much for Stephen and Jens. Jens, are you the author of the two papers that you suggested? I have read your papers and I am interested in your works. Do you have detial reports about the issue? Thanks very much :)

Reply to
grant0920

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