18-bit ROM in verilog

Hi group

I'm trying to infer an 18-bit rom to be put in a block RAM. I'm using a case statement and a clocked address as described by Xilinx. My ROM is

1024 words, so I was thinking that this could be done using only one BRAM, but the ISE 7.1 webpack creates two BRAMs in this case. Isn't it possible to fit more than 16 bits of ROM into a single BRAM ? I can fit 18 bits of RAM so why not ROM ?

-- Brian