Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
DDS generator with interpolated samples for Spartan3E development board
I've read the Wikipedia article about Direct Digital Synthesis ( ) and building a DDS generator with a FPGA, which interpolates between adjacent entries in the lookup table, looks like some fun. This...
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problem interfacing AD9510 via serial controller
Hi all, I'm trying to implement an analoge capturing project using Xilinx sx55 fpga and AD9510 as ADC. But I'v difficulty to program AD9510 clock distribution IC via its serial controller port to set...
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Which FPGA and memory to use? The eternal X vs. A question.
I need to build a sort of a simple video processor to drive a TFT LCD screen in an embedded system. The plan is to use a small and cheap FPGA with some memory. Low cost is very important, so fast SRAM...
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the FPGA gate way
hi all: Recently i'm doing the FPGA gate way. I have a smsc netcard(MAC +PHY). My main task is the gateway can receive and transmit the data package with the smsc chip. Generally this task is well...
 
Pin assignment with Quartus II for PCB placement
Hey folks, I'm working on a PCB that will have an Altera FPGA (Cyclone II in 672 ball FBGA). There is no code to be loaded to the FPGA yet so it makes testing the pin assignment hard (impossible?). On...
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virtex II pro - own core on plb with 2 interrupts
Hi, I'am trying to set up an Interface for an A/D - D/A Codec on an virtex II pro plattform using the (ppc) plb bus. What i want is to connect two interrupt pins from this A/D codec to an...
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selecting FPGA
I'm relatively new to FPGA. I've learnt vhdl and done few designs in xilinx Spartan II fpga, xsa v1.2 board. I've been involved in robotics and have designed some robotic system (basically line...
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usb cable driver
Hi All, I have a XupV2P board, ISE 9.1 and Windows Vista. I can't find the right driver for my USB cable to download my bitstream. Does anyone know where to find it ? Thanks, Andre.
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Help! I want give MGTREFCLK LVDS clock to GTP_DUAL (FPGA-Virtex5)
In UCF I write: NET "RefClkp" LOC = "AB4" | IOSTANDARD = "LVDS_25" ; NET "RefClkn" LOC = "AB3" | IOSTANDARD = "LVDS_25" ; In project: IBUFDS ref_clk_buffer (Test, RefClkp, RefClkn); But ISE swear in...
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SDRAM and S3E - is the example broken?
Did anyone get the DDR SDRAM work on the Xilinx Spartan 3E Starter board? I have tried to load the pre-built BIT file specifically for this board: s3e_starter_revD_mig_ddr. The readme file states that...
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For God's sake !! It did not work at all !!!
Hello buddies, I loved surely all of you have written herein and hence, I would like to thank everyone of you. BUT, I am an ongoing process of trail and error with such a trouble. So, my WebPACK 9.2i...
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Seeking help on xilkernel
I'm using a version of XMK provided by Avnet, for Memec Virtex-4 FX12 LC Evaluation Board. It includes a xilkernel demo, but I've found the sample code not working. I type nothing in the PC, but the...
 
student requiring assistance :)
I'm a final yr student undertaking a project which requires a microcontroller with an operating clk freq at 60MHz. My university has altera DE2 boards available, which to my understanding has...
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Using FSL with Interrupts
Hi all , Is it possible to use FSL read on an interrupt basis rather than polling? I have a scenario where i only want to read data using get instruction if there is data on the bus. Are there any...
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Synplify .sdc file
Hi, Is it possible to define clocks in the .sdc file of a design, while those clocks only appear in a peripheral or a core, i.e., clocks not in the top level of the design. Thanks, -J
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