Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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VHDL code for component labeling
Hi, I am a bit new to VHDL. Can some one please point me to component labeling (image processing) code in VHDL if there is any. Regards Rk
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16 years ago
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spartan 3e VQ100 serious question
How come in the pdf of the vq100 diagram, it shows something with 64 pins. This is odd because the spartan 3e sure doesn't come in a vq64, it comes in a vq100. Maybe they mean the vq100 has 64 pins...
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16 years ago
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Spartan 3e pin question
I have a question regarding the T9 pin of the FT256 footprint of the spartan 3e .. GCLK0 shares pin with the RDWR_B pin which is a configuration pin whitch according to the datasheet (p.97) has to be...
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16 years ago
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Newbee Microblaze system BRAM utlization confusion
Hi All , I am new to FPGA development and have learned VHDL using text books. NOW! that doesn't teach practical aspects! I am extremely confused with the following discovery - I am using Spartan 3...
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16 years ago
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Debugging designs that are running on FPGA
Hi I have a simple question. I have a design where the RTL simulation is working. Now I would like to see if the design also works then on the FPGA. The obvious way would be to use the JTAG interface...
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16 years ago
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FPGA Board design basics
Hi, I have been developing applications in Xilinx FPGAs using VHDL for the past 3 years for a small company in Virginia. As our designs are getting larger and more complex, the off-the-shelf boards we...
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16 years ago
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Xilinx RocketIO problems
Hi. I am trying to establish a communication between two RocketIO driven Virtex2P FPGAs. I am currently simulating the design running into the following problem: When I set the RocketIO Transmitters...
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16 years ago
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Drigmorn1 User Manual
First cut of the user manual for Drigmorn1 is now available here We are planning an update of this with some more photos and diagrams to clarify bits and pieces in a few weeks. As always anything you...
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16 years ago
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I try to Tri-Mode Embedded EMAC
hello I will be trying to [Tri-Mode Embedded EMAC] except EDK tool. Can I implement only by ISE 9.1i tool ? Does anyone have a sample project?
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16 years ago
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Initializing Micron DDR2 Memory
Does anyone know a way to initialize DDR2 memory models from Micron with data....easily? I have 16 DDR2 SDRAM models connected in a 2 Gigabyte SODIMM configuration. The problem I am facing is that our...
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16 years ago
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Poor quality Xilinx boards ? Your experience ?
I just got a Digilent Spartan3E board & tried to load a bit file using webpack 9.2 IMPACT says no USB cable found. Then I tried one of the JTAG3 cables from Digilent. IMPACT can see the cable but...
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16 years ago
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Craignell and Darnaw1 Website Updates
Pictures of the new issue PGA Darnaw1 on our website Main difference is the more standard 2x7 2mm JTAG and Serial Flash programming headers allowing our Prog2 cable and the Xilinx cables to be used...
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16 years ago
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Chipscope 7.1 and JTAG TAP
Hi I am using Chipscope 7.1 and I have a VirtexII xc2V6000 with a Instruction width of 6 bits. I have a design for which I had automatically generated a JTAG Controller. I can successfully sythesize...
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16 years ago
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sobel in vhdl
Hi people... I am trying to find a vhdl code for 3x3 sobel algorithm to implement on a Spartan 3, FPGA. I have found many papers on the subject but they are all from a high level of abstraction and...
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16 years ago
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Xilinx : Incorrect PACE file generation from schematic
Hi all, I am using Xilinx 9.2i schematic entry to design a simple clock circuit. The schematic uses come components that i wrote and i have added a counter from xilinx library. WHen i implement the...
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16 years ago
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