Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Video processing courses
Hello, I am an FPGA designer and I need to get more general knowledge in the field of video and image processing. Are there any courses that you can recommend? thanks and best regards, Karel
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16 years ago
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Xilinx XST questions
Hi all i have a series of questions regarding the XST capabilities (read: incapabilities). It all started when i had completed this nice multi-port register file code that used MxN BRAMs for an...
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16 years ago
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Core Generators...
hi... Im a novice in vhdl based design of fpgas'... I want to know 1. what is the use of core generators? 2. What are xilix primitives and cores? 3. what is the adv of using core generators over std....
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16 years ago
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TechXclusives from Xilinx
Hi all, Does anybody knows where are the web page of "TechXclusives" subject. It seems they've disappeared from Xilinx website. Thanks.
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16 years ago
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Spartan 3 FPGA verification via readback
Hi, I have a custom made FPGA board with Spartan xc3s1000 -4 fg456 on it. There is this strange behaviour of different bitstreams that made me to turn on the verify option while configuring the FPGA....
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16 years ago
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Re: FPGA Project Support
Hint, some people pay to get their homework done. Works great since they are likely to become a regular customer...
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16 years ago
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Centos 5.1 linux, Xilinx 9.2, Spartan 3E-1600 board (USB) programming
I have a 32-bit (x86) Centos 5.1 installation with Xilinx Webpack 9.2i.04 and EDK 9.2. I first started with Xilinx AR #22648. (i.e., I downloaded install_drivers.tar.gz) I hadn't payed much attention...
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16 years ago
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Darnaw1 - PGA FPGA Module
FAQ page page for our Darnaw1 now in place with some of the common questions answered. It's here As a reminder the Enterpoint Team are now on holiday until early January and sales and support emails...
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16 years ago
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cable IV and platform USB cable API now officially public
Hi it seems that Xilinx has promised to publisch (finally!) the programming APIs for cable IV and platform USB cable. this is not official but the universal scan last version includes notes that they...
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16 years ago
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video capturing+ filter + vga output
Dear All, I need to do the following: 1. Capturing 10 bit monochrome video 2. Recursive Filtering 3. Display the output to a LCD 4. Optionally sending the output to Ethernet Can you refer development...
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16 years ago
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DQS contention with ddr_sdr from Opencores
Hi, Has anyone used the ddr_sdr core ( on real hardware ? This core only uses the DQS lines for writing to the memory, and sets them as outputs. Therefore, during reads, both the FPGA and the DDRAM...
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16 years ago
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PowerPC & Spartan-3E Embedded Processing Development Kit - SP3E1600E MicroBlaze Edition
Hello, I want to know if the EDK included with the Spartan 3E Embedded Processing Development Kit - SP3E1600E MicroBlaze Edition can be used ONLY for MicroBlaze development, or can it also be used for...
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16 years ago
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Xilinx Spartan 3 JTAG issues
Hi, I have a XC3S400 based design with an XCF02 and I am finding I can't program the FPGA unless I power cycle it first. If I program the XCF02 it works fine - I'd rather program the FPGA for testing...
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16 years ago
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help with rising edge matching
Hello, I'm trying to write VHDL code that detects when two signals both rise fro zero to one at the same time. Do you guys have any idea on how to do this FPGAguy
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16 years ago
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Routing Vccint on four-layer PCB
I'm not very experienced at SMT PCB layout, but I'm trying to design a four-layer board with an XC3S50A-4TQG144. I'm using inner layers for 3.3V (Vcco, Vccaux) and GND. Am I asking for trouble if I...
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16 years ago
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