Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Free Seminar on SystemVerilog, Bangalore Jan 5th
Free Seminar on SystemVerilog, Bangalore, Jan 5th mailto: IEEE 1800, SystemVerilog is a major extension to Verilog-2001, adding significant new features to Verilog for verification, design and...
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16 years ago
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Where are the LCD or OLED bitmapped displays?
For the next-generation clock box (1 Hz to 1.5 GHz with ~50 ps jitter) I need an LCD-backlit or OLED display, 128 x 64 bits, single or multiple colors, about 2 inch diagonal. OSRAM had a nice OLED...
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16 years ago
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Split Plane
Hi I am designing an 8 layer board with a Virtex 4 device on it. I will hav 2 solid ground planes and 2 split power planes. If I have a signal plan that is between a ground and power plane will it...
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16 years ago
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no SystemACE on Xilinx Spartan 3A 1800 DSP in EDK 9.2.02
In Xilinx EDK 9.2.02, when I select the Xilinx Spartan 3A1800 DSP Starter Kit, the base-system-builder doesn't give me the option of adding the SystemACE peripheral to the hardware environment. In a...
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16 years ago
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State machine with stack to implement "subroutines"
Hi All, Playing with the Spartan 3E Starter Kit reference designs, I've found the following "Exercise" in the "Initial Design - LCD Display Control). Exercise: Implement a hardware state machine which...
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16 years ago
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xilinx PAR runtime and synplify synth runtime
Hi, I am using Xilinx ISE for PAR (from edf to bit file). and synplify tool for synthesis (to generate edf). Is there some thing like incremental PAR or incremental SYNTH. Please give some reference....
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16 years ago
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Can i verify RAM content with ISE simulator?
Hello from Diego Italy Another newbie question I'm using XilinxISE 9.2 on a Spartan3 XC3S1500 I would like to implement a simple dual port ram using the fpga block ram resources. After setting enable...
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16 years ago
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How to inhibit a timing warning
My Altera Verilog design is clocked at 50MHz (20ns period). Every 60ns, a data word is read and manipulated by combinational logic to give: one output word which is read after 20ns one output word...
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16 years ago
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a newbie question
Hello everyone ,I am totally new on this group ,and the subject ,sorry if thoses question are alredy answered. I am very , very much interresred in old computers particularly in dec pdp8 and pdp11,and...
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16 years ago
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JTAG chain detects Xilinx FPGA XCV150 instead of XC2S150...
Hi members, I developed a Spartan-II (xc2s150-5pq208) based card. I also installed Xilinx Flash (xcf01s) there. Unfortunately when I detect these chips through JTAG, I found Xilinx Virtex (XCV150)...
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16 years ago
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what is the difference between system side XAUI and line side XAUI?
would someone like to give me some explanation about the difference when XAUI work as line side interface or in system interface? i am much puzziled about this concept. thanks a lot
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16 years ago
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Architectural level CMP simulators
Hello everybody, Does anybody have any idea of a multiprocessor simulator. I have worked with uniprocessor architecture simulators based on simplescalar. Please suggest some CMP simulators which are...
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16 years ago
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Spartan 3E 3.3V configuration reverse current situation
Hi, as explained in the note : the use of 3.3V for configuration results in a reverse current which needs to be sinked by the power supply .. can the two resistors R3 and R4 in Figure 1 at used to...
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16 years ago
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Initialization of arrays
How does one initialize 'nibbles' in verilog the same way as 'longreg' is initialised .. ? reg [1023:0] longreg = 576'h555555555555555D00014AB7AE08002143658709800054; reg [3:0] nibbles[0:256];...
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16 years ago
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Xilinx EDK 9.2 problems under Centos 5
I installed Centos (linux) 5.1, Xilinx Webpack 9.2i.04, and EDK 9.2.02. However, when i launch 'xpsgui', I see a bunch of warning messages in my shell-window: QPainter::begin: Cannot paint null pixmap...
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16 years ago
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