Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
Timing constraints not applied, ISE & SynplifyPro
Hi, I'm a new synplify pro user. This tool seems to be much powerfull than XST for apply timing constraints. But there is something I don't understand : in the synplify pro report, I can see all my...
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Resource utilization broken down by hierarchy?
Hello, I am interested in looking at the resource utilization of a design I am working on broken down based on the RTL hierarchy of the design. I am using a Virtex-II Pro part. I have seen in the past...
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FPGA evaluation board with > 32K slices
Hi We are looking for an FPGA evaluation board to get a simple RISC processor running. It should have at least 32K slices and I was thinking of buying a Xilinx Virtex board. As synthesis tool we would...
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setup ETHERNET UDP link suing spartan-3E starter kit
hi, i need to 100BASET connection with a PC using xilinx spatan-3E board and lan83c185 chip.i need a bare system just to send some predefined UDP packets without using a Soft processor . if any one...
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Is it possible to define an Integer so it could be incremented and return to 0.
First of all, sorry for my English. What I want is: variable int : integer range 0 to 64:=0; begin process begin int := int + 1; end process; And the values: 0 1 2 3 4... 64 0 1 2 3 4 5.... But the...
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VirtexE LVDS driver
Hi to all, I am confused about one thing that if I want to use LVDS in VirtexE, should I feed the Vcco of the desired bank with 2.5 V. Is it applicable if I feed the bank by 3.3 V? What about playing...
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Feedback on Stratix III
Hi everybody, As Altera claims that Stratix III engineering samples are available today for some customers who subcribed to the early avaibility program, I am very interested in the 1st feedback from...
 
Power up Behavior of Virtex5 IOs
Hi, I have a design which has Virtex5 LX30T. On a particular IO, I have a external pull up of 4.7K, which connects to another device. I notice that at powerup that IO is driven down for 30msec before...
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How to view resource utilization by hierarchy?
Hello, I am interested in looking at the breakdown of resource utilization for a design I have done in a Virtex-II Pro (in ISE 8.2), broken down on based on the design hierarchy. I've seen in the past...
 
Place-and-Route : Intel vs AMD
Anybody heard of a recent benchmark comparing both Intel and AMD high- end processors regarding their Place-and-Route (PAR) performance? All I can find is a 2005 intervention here stating that AMD...
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Connecting different FPGAs using LVDS
Hi, I am trying to connect a Virtex4 and a VirtexE FPGA by LVDS signals. When I look through oscilloscope I see a good signal however on Chipscope I see glitches. I am trynig to operate at about 1...
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Cant capture data with Chipscope 7.1
Hi I have a simple VHDL counter modul that I wanna debug with Chipscope 7.1 on a Virtex II board: library IEEE; use use entity top is port ( clk : in std_logic := ?0?; cnt : out std_logic_vector(3...
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Purchasing IC components at a good price
If you are looking to buy components I have a friend works in class-ic and she will give you a good price
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XAPP924 Doesnt work
Hi All , I new to FPGA development tools from xilinx. I am following an application note number XAPP924 to use EPC module to inteface SMSC91C111 with a microblaze ( the application note is for PPC I...
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Multiple UCF support in Xilinx ISE
Hi, I need to know is it possible to add multiple ucf files in an ISE project? I tried to do this by splitting the original ucf file into two and added it into a project. The tool compiles only one...
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