Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Timing Analyzer hangs
I am using Xilinx ISE 9.02. When I invoke the Timing Analyzer, go to "Analyze" on the pull-down menu, and then further select "Against User Specified Paths ... by Defining Endpoints" the tool just...
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16 years ago
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Basic FPGA question about Reset
Hi I have a very basic question. I have a design that has a clk and reset input. I know that I have to connect the clk and the reset inputs to the corresponding pins of the FPGA. But how can i now...
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16 years ago
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Quartus II Incremental compilation?
The Quartus II handbook says that its Incremental compilation feature has the ability to iterate rapidly during the design and debugging stages. What exactly does this mean? Is this feature similar to...
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16 years ago
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V5-SYSMON : MAX6043 suitable?
Hi all, In UG192 Xilinx proposes to use a MAX6043 Reference IC as a supply for the System Monitor section. But I couldn't take the System Monitor into operation, because the REF- Voltage reached only...
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16 years ago
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gaussian filter in Altera FPGA
Hi all, I'm a new guy in fpga. I need to implement a GMSK in altera fpga. I plan to design a gaussian filter but I don't know how to do it. Can i implement the gaussian filter by using FIR filter...
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16 years ago
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Virtex-4 Embedded Tri-Mode Ethernet MAC Wrapper v4.4. 10base-T trouble
I m trying Virtex-4 Embedded Tri-Mode Ethernet MAC Wrapper v4.4. ON tri-mode 1000BASE-T /100BASE-Tx is success on TCP/IP commnunication. BUT 10BASE-T is bad communication. Only one ping send , but...
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16 years ago
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User inputs into Spartan-3E starter board?
Hey all, I need to input 2 signals into my spartan development board. These will be 5V(+/-10%) signals which I am running through 500 ohm series resistors for protection per question is, where can I...
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16 years ago
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Question on FPGA
Does Xilinx have any multicore FPGA ?
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16 years ago
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speed... CORDIC vs. pure arithmetic expression
Hello! I'm student, planing to work with FPGA for my thesis. Totaly unexperienced. Here I'm wondering about the speed. Don't feel the speed of multipliers, shifting, adding,... My plan is to implement...
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16 years ago
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help me about this error
Downloading Bitstream onto the target board ********************************************* impact -batch etc/ Linux ist SuSE 9.2 Starte impact ... Release 8.2.02i - iMPACT I.34 Copyright (c) 1995-2006...
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16 years ago
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All things ahead, planahead
I am looking at the Xilinx Ahead tools. I was told that there will be a "light" version included in the next release of ISE. If you have used these tools with the more recent ISE, Synplify, or other,...
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16 years ago
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FPGA Configuration using Multiple PROMs
Hello all, In my recent projects, I was using the V4 device (quite a huge one) and it required two 32MB Platform Flash to configure. To generate the corresponding MCS file, I pulled in two 32M in...
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16 years ago
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DCR_INTC usage in EDK - where is SR18804?
I'm trying to get the DCR interrupt controller working in EDK 9.1 with xil_kernel on a V4FX12. Hardware builds fine, but I'm not sure how to configure the software platform settings and so forth. In...
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16 years ago
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ieee_ proposed library
Hello all, I am trying to use some of the proposed functions by IEEE which are still awaiting approval. I am getting the following errors **Error: C:/Modeltech_pe_edu_6.3c/examples/util_top.vhd(58):...
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16 years ago
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Complex Multiply
I am trying to write a sunction for complex multiplication of 2 complex numbers function complex_multiply(a : signed; b: signed; c : signed; d: signed) return signed; (a + bi)(c + di) = [ac - bd] +...
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16 years ago
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