Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
[paper]?FIR on GPU,CPU, FPGA, ASIC
Hi, I am looking for a paper that compare the achieved performance from implementing general a N taps FIR filter on CPU, GPU, FPGA and ASIC i googled not much in return thanks
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Chipscope Inserter to Chipscope Analyzer
Hi, does anyone know if it is possible to create a Chipscope Analyzer Project including alle Trigger and Data Port names from a cdc-file? Greetz Helmut
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How is FIFO implemented in FPGA and ASIC?
Hi, Could anyone explain why FIFO is difficult to implement in FPGA and ASIC? and how is FIFO implemented in FPGA and ASIC. Thanks, Wei
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Xpower decoupling network summary
Hi, in the help file of Xpower it says that the standard report contains: A standard report contains: Power Summary Thermal Summary Decoupling Network Summary Footer BUT ... my report dosent display...
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CPLD Pad File
I am trying to generate a CPLD pad file using a dummy module and ucf. Translate process gives the following error: ERROR:NgdBuild:605 - logical root block 'test' with type 'test' is unexpanded. Symbol...
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SRL16x2 in Virtex5
Hello, I have a design where I need a couple of 16-bit shift registers, two bits wide. According to the "Virtex-5 FPGA User Guide", it should be possible to implement one of these in just one LUT6 in...
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When will Xilinx Webpack and EDK support Vista/64?
I'm pretty annoyed that the iMPACT program (download/program) is unusable under Vista/64. When will this be fixed? Also, Xilinx EDK 9.2 doesn't run under Vista (32 or 64-bit.) (The Cygwin component...
 
Quartus-II 7.2sp1 and Systemverilog Assertion SVA?
I tried synthesizing a Systemverilog-RTL file in Quartus-II 7.2sp1. The synthesis-engine doesn't seem to understand SVA (systemverilog assertion) syntax. property prop_x; @ ( posedge clk ) // disable...
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Using PECL inputs and PLL's in ProASIC Plus.
Hello, I am trying to use the PECL inputs of a ProASIC Plus APA075 device, independently of the PLL blocks. The two PECL inputs (one on each side of this device) can be used independently of the PLL...
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Two's complement Coregen gone?
Hi, I'm a systems engineer and not the direct FPGA guy, but I'm fairly involved in the implementation of my DSP algorithm on our Virtex-II platform. Our current code uses the 2's complement block IP...
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Speed of remote JTAG with Quartus jtagd on linux
I am driving 'jtagd' on a Linux box remotely from a PC to access a ByteBlasterII cable. The client and server PCs are both plenty fast (the server was my desktop until recently and did the programming...
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Xilinx ISE9.2 iMPACT manual
Is there a complete manual for iMPACT ISE9.2 ? Can't find it. Brad Smallridge AiVision
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Chipscope compatible with Synopsis or Cadence sythesise tools?
Hi I have an VHDL core that is sythesizeable with the following tools Synopsys Design Compiler Cadence Encounter RTL Compiler Until now I was using XST for sythesis and it seems when I try to run...
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effect of xray on fpga electronic circuits
Dear All, As an assignment I have to design a CCD Sensor based FPGA digital Camera. However, the Camera will be exposed to XRAY (It will be placed behind an Imaging Intensifier). Does anybody know how...
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CynApps Cynlib
Does anyone have a copy of Forte Design (CynApps) opensource Cynlib? I appreciate if you can send me a copy. -- Amal
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