Hi,
I generated two FIFOs using Xilinx ISE CoreGen.
Both FIFOs are 64-bit wide, but one FIFO depth is 16, the other is 64.
After doing the mapping, I was surprised to find that both FIFOs use the same amount of BlockRam.
I cannot understand the reason since the 16-depth FIFO will definately use less memory than the 64-depth FIFO.
Please give some idea about this. Thanks.
amount of BlockRam.
less memory than the 64-depth FIFO.
Surely this isn't homework. Memory is only available in certain widths and certain depths. If you exceed either of those two, more memories will have to be used, even if the first one is not fully utilized. Your wide bus is the limiting factor here, not the depth or the total number of bits used.
Have fun,
Marc
amount of BlockRam.
less memory than the 64-depth FIFO.
XST tends to use block ram even when it doesn't need to. In the 16 deep FIFO use a directive to force it to use LUT RAMs. The example below has directives for both XST and Precision, the // synthesis is XST, the // pragma is Precision.
reg [WIDTH-1:0] ram[15:0]; // synthesis attribute ram_style of ram is distributed // pragma attribute ram block_ram false
For the 64 deep FIFO block RAM is the better choice. For depths of 16 the trade off between LUT Ram and Block RAM is that LUT RAMs are generally faster and easier to place, Block RAMs are cheaper. The minimum depth of the Block RAMs is 512, (512x36), so if you are using them for FIFOs you might as well make them 512 deep.
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