Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
Endpoint Block Plus v1.5 example design
Hello, I'm trying to get running the example design coming with Endpoint Block Plus v1.5. I have generated the core with ise's coregen and compiled the smartmodel libs also with with ise. But when...
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OV7660 CMOS camera
Hi all, Am working with this camera. wanted to know if anyone else has worked with it before. I have a set of register settings and want to know if that is right. i am working towards getting a RGB...
 
Fixedpoint Multiply/Accumulate in DSP48
Hi, am a little confused as far as the capabilities of the DSP48 go. I would like to implement a 18x35 MACC in (hopefully) only two DSP48. The 18 bit coefficient is a 0.18 fixed point number. I.e....
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Initialize RAM in IGLOO
Hi all. I am making a design for an IGLOO FPGA from Actel and I have have added a Two Port RAM component in Libero (the development tool). Here I can choose to "Customize RAM Content" and have...
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Craignell FPGA DIP Module
Craignell user manual is now available also have UCF file available for the CR40 and the other sizes to follow shortly. John Adair Enterpoint Ltd.
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Adaptive Best Practices
AJ Square's best practices consists of proven methods and processes that have developed to share with our customers and partners so that you can benefit from the hundreds of successful online projects...
 
problem simulating in modelsim - swiftpli_mti.dll
Hi There, I am getting the following error in modelsim when I try to simulate some thing. # Loading C:Xilinx92ismartmodel tinstalled_nt/lib/ swiftpli_mti.dll # ** Error: (vsim-3193) Load of...
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Virtex-4 driving a 5V CMOS
Hi all, I need to drive a 5V CMOS input from a 2.5V Virtex-4 bank. Is there anything wrong with simply using a pullup to 5V? The speed doesn't matter. Thanks.
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XST_BUFFER_TOO_SMALL
Hello, I am now using DeviceReadFrame function on Xilinx EDK9.1 sp2. But it returns "XST_BUFFER_TOO_SMALL". According to the reference, it says that Reads one frame from the device and puts it in the...
 
Random Number Generation in VHDL
Hello members, I would like to know if VHDL already has functions defined to generate Random Numbers. If not, which would be the best algorithm for generating random numbers for implementation on an...
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EDK 9.2i install issues in Linux
I know Xilinx does not officially support anything other than RedHat Enterprise Linux, yet so many people have installed it on other versions such as Ubuntu, Gentoo, etc. I am trying to install it on...
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microblaze question
I'm investigating if the microblaze is an option for a project where physical space is extremely limited. Perhaps somebody can answer the following: 1.Is it possible to use the microblaze in a...
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Craignell FPGA DIL Module
Our Craignell webpage now has the schematics for the Issue2 40 pin version on it for all that have asked. Webpage is here We now have a limited stock of the programming adaptors for the Craignell...
 
How to choose an FPGA for High speed applications
Hi all, I want to choose an FPGA for a High speed appliction so which one to go for either for Xilinx or Altera. But i am vey much familiar with xilinx devices. And in the design the gate array will...
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CFP: DATICS 2008 - Design, Analysis and Tools for Integrated Circuits and Systems
Apologies for any multiple copies received. We would appreciate it if you could distribute the following call for papers to any relevant mailing lists you know of. CALL FOR PAPERS...