Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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MG Leonardo Synthesis Options
Hello, does anyone have an answer to the following two issues on using leonardo: 1. How can I see the exact functionality of the the cells Leonardo produces in its RTL Schematic, after reading my...
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16 years ago
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A way to limit the data path delay
Hello, I have a problem with apparently no issue. I use a V5 and I have a problem with the data path delay of a net. This net is used everywhere in my design and particulary in fixed blocs. The fanout...
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16 years ago
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Minimum Oscillator Frequency
Hallo to everyone, I should develop a system which outputs a pwm signal into a filter to obtain a sine at 500 Hz which will command a class D amplifier. I was considering to use dds compiler to...
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16 years ago
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Possible CRC error on XC3S400 - now what?
Hi, I'm trying to configure a Xilinx Spartan 3 s400 through JTAG in a new prototype but I'm getting some weird results back while programming it. I hope somebody with more experience can help me out....
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16 years ago
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4-bit table look-up
Hi I have a simple question, whats the best way of designing a lookup table which is 16 bit wide in VHDL and for sythesis. It receives 4 input bits and depending of the values 1 bit will be selected...
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16 years ago
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A video tutorial: The Xilinx FPGA Editor
Hello all, For all those who know that the Xilinx FPGA Editor exists, and maybe that it's good for something, but are reluctant to try it out (for obvious reasons): I've made a short video guide,...
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16 years ago
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forcing "Unused IOB Pin -> " from .ucf
Hi all, Are there any way to force some generate programming file from .ucf ? 1. Generate Programming File -> General Options -> Create Binary Configuration File -> checked 2. Generate Programming...
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16 years ago
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OFFSET In and hold time
Hello, I have a question about the OFFSET In constraint. To my mind, OFFSET In is the same thing that the set-up time. But what about the hold time ? If I want to have a bigger hold time, I need to...
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16 years ago
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Server configuration for Virtex5
Hi, Our company is looking to buy some Linux servers for design implementations of Virtex5. So I was wondering if there is any optimum configuration that I can use to decrease my run time of the...
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16 years ago
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Call For Papers: FPL 2008
FPL International Conference on Field Programmable Logic and Applications Call for papers Submission Deadline -- March 16, 2008 Acceptance Notification -- May 21, 2008 The International Conference on...
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16 years ago
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Bitstream verification through readback
Hi, i need to know is it possible to readback and verify the loaded configuration in the FPGA after the GSR is deasserted and the FPGA is up and running with the loaded configuration? I am suspecting...
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16 years ago
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Scaling data
Hello All, I am using the UNIFORM procedure in VHDL to generate random numbers. UNIFORM generates random numbers in the range 0.1 to 0.99999. I wish to generate random signed and unsigned numbers of...
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16 years ago
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Internal signal names in ModelSim
I have synthesized and implemented my design, and I was going to simulate post-route using ModelSim. The problem is that all internal signals have been renamed, and I can't match each signal with the...
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16 years ago
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Loading from Compact Flash on ML310...
Hi everybody, I have written a very simple code for microblaze on Virtex II-Pro (XC2VP30 on ML310 board) which basically writes something to STD-OUT (through uart). When I load the design to the FPGA...
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16 years ago
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spartan3a support DVI ?
spartan3a support T.M.D.S. signal standard ,but since DVI signals are 1000M or higher ,how can receive data from DVI ?
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16 years ago
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