Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Timing Constraint not met
Hi I put a timing constraint in the UCF File where i asked for a minimum frequency of 35 MHz (29 ns) but unfortuatenly XST tells me that the ratio was not met and the actual ratio is 38 ns. I have...
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16 years ago
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Problem in assignment of pins in PACE
Hi all, I have recently just generated HDL netlist from System Generator 9.1 and I have began assigning the pins in PACE for my design. Although I have assigned most pins as well as the clk, I have...
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16 years ago
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Strange "Style guide" requirements...
I've been working as a 'consultant' / sub contract engineer with a strong emphasis on FPGA work for about eight years now (after a previous eight stint as a permanent employee with a large Telco). I...
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16 years ago
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Looking for a development board
Hi everybody , I am looking for a development board. My intention is to devolp a DSP application so ideally should contain : -xc3s500e-pq208 -ADC
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16 years ago
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How to get Map Repoprt after System Generator postmap estimation
Hi all, I have done some resource estimation while doing my design on System generator 9.1. But it beats me where to get the map report after I have done post map estimation. I will appreciate some...
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16 years ago
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impact bug or wrong interpretation of xsvf layout?
Hi, While debugging my xsvf parser for ft2232 jtag programmers I experience some really odd behavior; if I swapped my buffer and then send (essentially) 'junk' to my device it would actually boot,...
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16 years ago
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Weired Distributed Memory behaviour
Hi As mentioned in an earlier post, I need an asynchonous instead of a synchronous data memory. The design was working with the BRAM, but the data was delayed by one cycle. So one would expect when...
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16 years ago
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I/O mode to use for USB ..?
Which I/O mode like LVDS_25 etc.. is suitable to interface USB on a Spartan-3 FPGA ..? (I know the single ended signaling within USB). The idea being to eliminate any external usb transceiver.
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16 years ago
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What does "Continuous Sample times are not allowed" mean in SysGen 9.1?
HI all, First , I would like to thank the folks who have helped me to solve my last problem of optimizing my Digital Down Converter design to shrink 400% and fit one Virtex chip. Apparently, all I did...
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16 years ago
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Marking Flase paths for Timing Ignore + Virtex 2 Pro support
Hi, I have two questions. ============================================== Marking False paths for timing ignore in a multiple clock design: =============================================== I have a...
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16 years ago
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Prom alternatives for xilinx
We are want to use a spartan 3E in the very small chip scale package because of space constraints. However the 4 MBit serial prom for this device is almost the same size as the whole fpga. Does...
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16 years ago
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ML410 and documentation on ALi M1535D+
Hi everybody I had the intention to buy an ML410 board but the local Xilinx reseller told me that there is a problem concerning the ALi M1535D+ - there is no documentation given with the board. But in...
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16 years ago
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Shutdown parts of core logic on FPGA
Hi NG. I would like to know if it would be possible to shutdown (cut the power) from some parts of the core logic on an FPGA while other parts are still running? Like, could I have an internal timer...
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16 years ago
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beleive
I can hardly beleive, that when a single FPGA may cost up to 2000$, there is no space for a few hundred kilo- maybe megabytes of information in an age, when a terabyte costs around a few 100$s. Or...
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16 years ago
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function/process to generate sine and cosine wave
I would like some guidline on writing a function or process to generate a sine wave and cosine wave. I want to include this into my library. Each time this function/process is called, I would like...
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16 years ago
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