Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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ADPCM IP Core
Hi, For one of my projects, I am looking for ADPCM IP core. I found a previous thread and a Xilinx release note which says that the core is available from Xilinx. But I could not find it. Could anyone...
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16 years ago
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V4FX: LVCMOS25 vs LVCMOS33 output buffer
Hi all, Is there a difference which one is instantiated when the actual VCC in the bank is 3.0V? Thanks, /Mikhail
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16 years ago
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Interrupt Handler page missing in from software platform settings in XPS 9.2i
I am trying to port an application from ISE/EDK 8.1i to 9.2i. Everything is going well except for one thing - the page in Software Platform Settings for specifying the interrupt handler is missing. To...
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16 years ago
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Post PAR simulation is successful but still fails on the board
Hi, I am using a Virtex II development board and am doing some work with a little system on a chip. I am using onboard block RAM as both the instruction ROM and RAM for programs. I was going along...
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16 years ago
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From ASIC RTL to FPGA, what are the things I should take care of?
I have a project to prototype an ASIC design on FPGA. What are the things I should do? Here is some of my concerns: 1) I understand FPGAs usually have 4 look-up table. Should I rewrite the ASIC...
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16 years ago
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scanf problem in EDk 9.1i (Microbaze)
Hi, How to read an integer from hyperterminal onto a microbaze using EDK 9.1i. Im trying it using scanf but its giving me errors. here are the lines of code im trying to achieve the read....
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16 years ago
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Virtex5 BUFR min frequency
Hi all, I've a question about BUFR primitives. I read in the datasheet that BUFR can distribute their output clock on clock regions, and have the availability to divide the input clock frequency by an...
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16 years ago
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Which Linux Distro to use for Xilinx tools
Hi, I Love Linux, but currently i have to boot in XP because of xilinx toolset (ISE, EDK, sysgen Matlab, chipscope etc) May any body tell me , Any Linux Distro (other then commercial , like redhat, i...
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16 years ago
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FPGA Programming solution
Greetings , I am trying to implement a solution for an FPGA that needs to be configured with two different programs because the whole system will operate in two different modes. Basically what I need...
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16 years ago
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MIG and Spartan3 for a 112 bit DQ bus (7chips x16)
Hello, Has anybody tried to use MIG with a Spartan 3 to generate a memory controller that has a big DQ bus? I would like to generate a core that controls 7 chips (x16), this results in 112 DQ pins....
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16 years ago
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Efficient division algorithm?
I'm going to talk to a potential new client about using FPGAs to accelerate part of their system. As part of what needs done there could be a significant amount of division(s) done. Previously I've...
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16 years ago
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Using Lattice ispLEVER with VHDL libraries
I am trying to pick up the Lattice ispLEVER tool and am having a bit of trouble with it in regards to libraries. I have several files for the various libraries I have written for my VHDL. In order to...
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16 years ago
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TCL testcase in Modelsim.
Hello, Does anybody have experience on writing TCL testcase in Modelsim? I only have VHDL simulation license of Modelsim, I used to write both testbench and testcase in VHDL. But I feel VHDL is not...
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16 years ago
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V4FX100 PowerPC PLB issues (and EDK 9.2)
Anyone ever run into an issue where the PowerPC can write to entities on its DPLB, but cannot read from them? I've added chipscope to the PLB and everything looks right from the control lines. I...
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16 years ago
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Define the primary clock with XST in VHDL
Hello Guys, How to specify with XST that an input of a VHDL entity is a clock ? I guess it is not automatic because after the XST logic synthesis, noone of my "process" have been synthetized ? thanks,...
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16 years ago
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