Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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canny edge detection
hai.. i am doing project in image processing using cyclone II fpga...i need the core of the canny edge detection for one of it's module..any one can help me..
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16 years ago
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Planahead IP export
Hi, I'm trying to insert an IP core generated by PlanAhead into our script-based flow, but map fails with Pack:679 error on several slices. The IP in question is a wrapper around the PCIe block plus,...
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16 years ago
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FPGA Editor Tutorial based on examples
Hi, I am looking for some good in depth tutorial on FPGA Editor. I have seen the video demos on youtube but they just give you intro to the tool. There are so many tutorials available on other tools...
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16 years ago
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Xilinx DCM for frequency synthesis -- newbie question
I'm trying to use a DCM on a Spartan 3E to synthesize a frequency of 8 MHz but see only a constant 2 volts on the CLKFX output. The google hits on this did not help. It must be a simple mistake; any...
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16 years ago
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Problem with PINs XC3S700A-4FG484
In the quick start tutorial, it says connect DIRECTION with PIN K13 (SW7 signal on board), but after browsing through ug300.pdf and s3a schematics, I don't see anything that remotely makes sense. I...
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16 years ago
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newbie seeking help to use xilinx spart-3a starter kit
Hello, I just received the package and it has the fpga board, usb cable, and power supply. I am am trying to it with Suse 10.2. I have installed the WebPack+SP4 softwares. Of course the kernel modules...
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16 years ago
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Actel FPGA programming using libero 8.1 generated SVF files
Hi Since version 8.1 Actel provides SVF programming file generation for A3 FPGA's but I have problems using those SVF files: For first testing i used Xilinx IMPACT as SVF playback engine, and I got...
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16 years ago
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Xilinx self-termination
Hi any info on ISE 10.1 ? maybe, HOPE really, Xilinx has done something to improve their software quality. It should be possible to write the GUI that doesnt self-terminate itself so often. I am...
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16 years ago
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Software Defined Radio on Xilinx Virtex 4
Hello, Let me right again in this forum on the same topic. But know in English. Whatever my English is very poor. I am working for about 4 month's ego with an ML405 Xilinx Virtex 4 board and I wanted...
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16 years ago
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How to use xilinx specific features from Modelsim Designer 6.3a VHDL
Hi All, I have started a test design in Modelsim Designer. I now have one entity written in VHDL and have placed this entity on a block diagram and added in- and out ports to the entity's signals. The...
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16 years ago
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Interview questions
Hi I just came across some interview questions for digital design, and would like to discuss my solutions with you! #Design a circuit to divide input frequency by 2 I could do this with a Toggle Flip...
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16 years ago
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Software Defined Radio auf Xilinx Virtex 4
Hallo, ich arbeite seit 3 Monaten mit einem Xilinx Ml405 Virtex 4 Board und wollte darauf nun mal ein Software Defined Radio (SDR) implementieren. Ich verstehe alles was auf SDR betrifft (Theorie,...
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16 years ago
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which IOSTANDARD to use for IO-bank in Spartan-3
Hi, We are currently designing a Xilinx Spartan-3 FPGA based tool that needs to communicate with a daughter card. Multiple variations of daughtercard exist, each of which have a different IO voltage (...
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16 years ago
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Reconfiguration (on the fly) using SPARTAN 3A
Hi all, I want to know whether it is possible to program Spartan 3a for a run time partial reconfiguration. If yes are there any detailed demo programs available? Regards, Parunoy
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16 years ago
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System generator hardware co-simulation interface
Hi, All! Need more info about system generator hardware co-simulation interface. Using JTAG for custom board very simply but extremely slow. How to support hardware co-simulation on custom FPGA boards...
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16 years ago
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