Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
sd card slave interface
Now I want to design a SD card,for special use,I must use fpga to implement the interface between host controller and NAND flash,can someone give me some advice if it is easy to implement it?And where...
4
4
 
Using dma_sg_v2_01_a component with plb_ipif
Hi, I would like to interface a custom DMA controller to the user_logic created by "Create or Import Peripheral" in EDK 9.1 tool and not use the simple DMA controller that can be included as part of...
 
Bus2IP_WR/RDCE XIO_Out/in32 EDK 9.1
Hello all, I am writing to one of the software programmable registers (slv_reg0,1,2..) on a OPB slaves in the system using XIO_out32 command. It was working fine for sometime. but recently when i...
1
1
 
Quicksim/modelsim
I am writing a testbench and one of the clock is a "gated clock" - meaning clock is clocking every time gate goes active. so say that gate pulses at time T. Then clock goes active at T+ 10uS for...
1
1
 
ICAP attached to Microblaze on Virtex 2-pro..
Hi everybody, I'm trying to partially reconfigure my device (XC2VP30 on ML310 board) through ICAP. I have my ICAP attached to OPB which is attached to Microblaze. In bitgen.ut file I have set the...
6
6
 
Why must a V4 be configured within 10 minutes of power up?
I was looking at the Virtex4 specs and notices a spec (Tconfig) that says you must configure within 10 minutes of applying Vccint. I don't plan on violating this spec, but it struck me as odd. Just...
5
5
 
ANNC: ADC to FPGA Interface Webcast
It's unfortunate that the webcast requires a propietary win32 plugin installation. Rather then just provide a plain straightforward video url.
5
5
 
ASAP 2008 Submission deadline extended till 5th March'08
Dear Colleagues, Please accept our apologies if you receive multiple copies of this CFP. !!! DEADLINE EXTENDED !!! New Submission Deadline: 5 March 2008...
 
Xilinx's microblaze hangs when a timer interrupt occurs after a "rand()" instruction.
Hi, I have implemented a Microblaze v7.00.b with EDK 9.2 on a Virtex 4 fx12. A timer (xps_timer v1.00.a) generates an interrupt which is relayed by an interrupt controller (xps_intc v1.00.a) to the...
6
6
 
Tomorrow at Embeded in Nurnberg: Portable XSVF player demo
Hi I was not sure if i can get a working demo ready but it looks it I did: it just shows a handheld device running embedded XSVF player executing some XSVF file from micro-SD card. Wi-fi support is...
 
SPI indirect programming using spartan 3e
Will it be possible to use indirect programming of an SPI flash for Spartan 3E in future releases of ISE ? Im using 9.2, and if i choose "Enable programming of SPI flash device attached to this FPGA"...
3
3
 
How to connect FPGA to a ASIC Board?
Hello Techies, I would like to use an off the shelf FPGA which I would be develpoing to test an ASIC or other FPGA. My questions is, 1. How do we connect the Output of FPGAs as Input of the ASIC and...
8
8
 
Viewing RTL schematic in Xilinx ISE
How can the RTL schematic of a VHDL design be viewed in Xilinx ISE 9.2? I just upgraded from 8.2 because I couldn't find it there (and the upgrade was long due anyway), but I still have not found it....
2
2
 
OPB_MDM as UART in a PowerPC design
Hi everybody, I work with a VirtexIIPro in a design with PowerPC processor. I have some problems with the opb_mdm to work as uart. My board has not RS232 peripheral, so I used a OPB_MDM and a PLB2OPB...
 
Preventing optimization in cross clock domain logic
In a situation where it is necessary to cross between two clock domains within an FPGA, I might use logic that produces an output toggle (toggle_out) on the 2nd clock in response to a single-cycle...
6
6