Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Synplify crashing
I am using the Lattice ispLever tool for their PLDs and I seem to be having trouble with Synplify. It crashes frequently and I don't see any particular reason for it. It doesn't correspond to any...
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16 years ago
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clock generation
hi i have a basic doubt in fpga implementation. i am new to this. i have made a stepper motor controller and implenting it on a DE1 board. i have no problem in simulation. everything is working fine....
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16 years ago
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Avnet/Memec V4FX12LC proto card and SysGen
Hi, Has anyone used this card with Xilinx System Generator to do hardware in the loop simulation. I can not find a board description file for it in the form that the System Generator wants. There is a...
2
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16 years ago
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FPGA's be afraid, very afraid, of my wife!
Hi recent events: 1) trying to use Xilinx Cable III (actually Amontec chameleon) to program actel PA3 on protoboard using DirectC 2) with big fights i got "random" results sometimes reading first...
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16 years ago
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Quartus 7.2sp2 memory exhaustion
Hi. I have Quartus 7.2sp2, MS Vista , and I have a project where I define ROM memory (with size 4096*32 bits). I define it in verilog file in "initial" section. When synthesing, quartus_map.exe...
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16 years ago
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HELP > Face/Edge detection on FPGA
Hi all I want to implement face detection on fpga Is there any free code available Or is there any code for edge detection available. Plz help I need ity very much.
3
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16 years ago
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Need info on systolic arrays in actual use
I need some references of where systolic arrays have actually been used in equipment or instruments. Thanks in advance, Marco ________________________ Marc Reinig UCO/Lick Observatory Laboratory for...
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16 years ago
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real to signed
How to convert real to signed. The range of real will be from -1 to 1, -5 to 5, -10 to 10 and so on. I would like to convert this range to a signed vector of bit width bw(generic). The data has to be...
9
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16 years ago
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DSP Ip Core
Hello all, I am looking for a free DSP Ip core (like the OpenCores C54). Have you some idea to look for ? Best regards, JSL
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16 years ago
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Is there any way to disable JTAG for Sptantan3AN
Hi, We want to make Spartan3AN as One Time Programmable. We want to program it once and then disable JTAG. Is it possible to do that? How can we do that? -- Goli
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16 years ago
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10 | |
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What demokit and VHDL compiler pair to buy
I got Xilinx free IDE running and even got some simple designs through. But there wasn't any Xilinx programmer/evaluation kit available from Farnell or Elfa. What is the problem. From where I could...
2
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16 years ago
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Software for FPGA-based PC scope
Hello, Although I am a newbie in FPGA design and have experience only with some simple designs so far, I am thinking of some more ambitious project and want to design a FPGA-based PC scope working in...
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16 years ago
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DCM Simulation : Input Clock Cycle Jitter
Hi Group, Just wondering if anyone has seen this issue. I am simulating a Xilinx FPGA design (RTL) containging DCMs. I get the following warning Warning : Input Clock Cycle Jitter on on instance *...
2
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16 years ago
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DSP newbie
I have written a process to generate sin wave as below. -- sine wave constants amp_sin : real := 10.0; phase_sin : real := 0.0 -- phase in radians samples_sin : integer := 1000; -- number of samples...
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16 years ago
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Making changes to custom IP in EDK
I'm using EDK 9.1i. I have created custom IP using "Create or Import Peripheral", modified the VHDL files, and then imported it into my project using "Create or Import Peripheral" once more. If I make...
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16 years ago
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