Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
Matlab, RS-232, Ethernet
Hi, I want to interface matlab with the Xilinx Virtex-II pro board. Intent is to give input from matlab to the FPGA and to read the ouput of FPGA in matlab. Problem is in interfacing speed. I need...
8
8
 
Virtex-5 FX when ? (III)
Hello Antti, Peter and ..., yep, meanwhile many, many months later - the same question... V5-FX? Thanks and greetings Udo
5
5
 
vhdl code realization
Hi everyone, I have a issue with fpga design optimization. Can any body explain me What is called "reorder path"? with any nice example with hardware realization. As per some book reference it says...
1
1
 
its regarding to the Max Frequency in xilinx FPGA
Hi, to all i am new to this group which a great place to share and find the more discussions environment. so my question is on xilinx virtex series FPGA's 1. every virtex series is having maximum...
4
4
 
Virtex-4 VLX25 DCM problem
Hi all, the following strange thing with Virtex - on the input I have base 24MHz, DCM generates 32MHz internally, and on one of the outputs should have 8MHz (32/4). It is a previosly designed product,...
13
13
 
New Release of VPR, Version 5.0 Beta
For those of you interested in research on the development of FPGA CAD and architecture, I am pleased to announce the release of new version of VPR, Version 5.0 Beta. This is a CAD tool suite...
 
opencores down ?
hi groups I notice that is down ... the very moment i need jop core... does anybody know if there is a mirror available somewhere ?
2
2
 
2nd CFP: DATICS 2008 - Design, Analysis and Tools for Integrated Circuits and Systems
Apologies for any multiple copies received. We would appreciate it if you could distribute the following call for papers to any relevant mailing lists you know of. 2nd CALL FOR PAPERS...
 
Hardware Cosim one wrong output and one correct output
Hi all, I have designed a DDC component with 2 outputs representing the I path and the Q path outputs. Simulation in Simulink works fine. However when I did hardware cosim, the Q path hardware cosim...
 
Cyclone III and Quartus 7.2sp2
Hi. Analysis and Synthesis for Cyclone III is SO slow.. One my design with about 30000 ALUTs was analysed and synthesed more than 12 hours and I finally breaked it. Target device was set to EP3C25F324...
9
9
 
Datasheet on Micron's secure products
Good morning, does anyone know hot to get a datasheet of a Micron's product under NDA? I've an account on but by clicking on My Sites -> Secure Product Sites, unfortunately, I don't see nothing. :-( I...
4
4
 
Danger of having JTAG TAP controller always enabled in Xilinx parts
Hi all, I am reviewing a design, which has a bunch of JTAG-enabled parts. Some of the these have TRST pins, others (Xilinx) don't. I came across some interesting read on this issue: So, my questions...
6
6
 
SiliconBlue enters the FPGA fray
Talk of devices from 1,792 to 15,260 logic blocks, and currents a little under Altera'a MAX IIZ (on a Logic Block basis). Not stellar Static ICc values, but reasonable - considering they have to fight...
23
23
 
ML523 power module schematics
Does anyone know how I'm supposed to get hold of the ML523 power module schematics? The link on the web site doesn't work. TIA, Rog.
3
3
 
Altera Quartus II v7.2 SP2 under openSUSE 10.3 (i686)
Did someone here have any luck with using Altera Quartus II v7.2 SP2 under openSUSE Linux 10.3. It seems to work fine under openSUSE 10.2 and Fedora Core 6. But when I try to start quartus (the main...
1
1