Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
Almost offtopic about HDL optimizing.
Hi. I see how Quartus synthesizer removes unused parts of algorithm implemented in HDL, optimizes it and so on. Other synthesizers probably do the same. My question is almost offtopic: is there any...
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Xilinx ISE Evaluation DVD 10.1 request...
Please, please, please fix the DVD installation-wizard, so that you can install the 32-bit (Webpack) tools on a 64-bit platform. (This goes for both MS Windows and Linux.) I really hate having to...
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Using xilinx XAUI core in Ethernet design. What is the exact frame format pass through XAUI?
We use xilinx xaui core in our Ethernet design, we choose XGMII as our internal interface. And now, I am confused. I found that the data between START(0xfb) andTERMINATE(0xfd) will all be transmit...
 
microblaze to blockram - Byte-Writes
I am trying to interface a 32 bit blockram to microblaze (spartan 3E), using the User-Address ip support in the "Create and import peripheral". I have instantiated a black box blockram 32x256 and it...
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Temporarely no answer on MEM32 Read request
Hello, At the moment I am designing a PCIe Card with Spartan 3E 1200 -5 and Xilinx PIPE Core. The firmware is almost done, but I have observed that from time to time a completion is missing for a DMA...
 
Is 32 bit Xilinx ISE Webpack compatible with 64 bit ChipScope Pro? ISE isn't seeing it when I try to add new source.
Is 32 bit Xilinx ISE Webpack compatible with 64 bit ChipScope Pro? ISE isn't seeing it when I try to add new source. I originally had the 32 bit ChipScope installed. ISE could see that and I was able...
 
infer block ram with mismatched port width
hi i have a question on how to infer a block ram with mismatched ports. as far as i found out with google and the xilinx manuals this is how to infer block ram with matching ports in read first mode:...
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Xilinx Pipelined Divider for V5?
Anyone know if Xilinx plans to support the Pipelined Divider for the V5? Is there an equivalent available, buried in some other Xilinx core? Thanks!
 
Cyclone III FPGA Starter Kit: As USB device? Using JTAG terminal without Nios2?
Hi. Got this board. Two questions. 1. Is it possible to use this board as prototype of some USB device without any solder rewiring? 2. Is it possible to have, let's say, nios2-terminal.exe on computer...
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VME 2 Ghz clock generator
Hi, I am loooking for a VME 2 Ghz clock/sync generator board. I find that: -VMETRO XCLK1 -Pentek 6890 Is there a board mixture of the two : clock generator + synchronous trigger @2Ghz ? Thanks!
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Design complexity in Logic cells - Virtex-5 FPGA
Hi, Some IP vendors gives the complexity of the device in terms of "LCs (Logic Cells)". How can I calcuate Logic cells from information available in Map report? ********** Logic Utilization: Number of...
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avnet virtex-5 lx eval kit ddr problem
We have two of these boards (with the LX50 ES), and both failed the DDR memory test with a build from the Base System Builder. We downloaded the test designs from the Avnet Design Resource Center, and...
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Could I develop a new gui using java based on the script language of ChipScope?
I found Chipscope is too difficult to learn for college students, it has too much options. I want to develop a simple gui software and using it in a 8086/8088 FPGA embedded system. For example,...
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Ann: New FPGA beginner's Video guide
Hi all, I have just released a new online Video guide called "The BurchED Getting Started with Xilinx FPGAs Video Guide" It is an easy step-by-step guide for FPGA beginners. I go all the way through...
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BRAM synthesis question
Hi everyone, While trying to build a simple VGA driver, I'm running into trouble getting my video-ram (actually, sample ram) to be synthesized as a dual port block-ram - it keeps wanting to use up 25%...
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