Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
BYTE shifter
I wanted to perform a byte shifting of a 24bit vector . the resultant vector is a 48 bit vector . the following is the functinality needed signal BV : std_logic_vector(23 downto 0); signal BYTE_SEL :...
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using mpmc ddr2 controller with an other processor
hi groups ! what is the best route in order to use an edk generated mpmc ddr2 controller with a custom processor (not microblaze, but gaisler leon3 or even picoblaze ; this is for edu. purpose...) ? I...
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counterfeit Xilinx ?
I got a batch of "Xilinx" Spartan XCS30 FPGAs from a Chinese seller, and am having problems with random failures at first power up. Sometimes it is a stuck I/O pin, sometimes a failure to configure. I...
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High speed memory read and transfer via rocket IO..
Hey, I want to read an 8bits data from a memory at 500MHz and want to send this serially at a speed of 4GBits/s. I am reviewing the documents. What are the possible solutions for that memory read...
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Raggedstone1 OEM Pricing now released.
We have now publically released the pricing for Raggedstone1 for OEM quantity pricing and for all those that keep asking we have added now an "I" option for OEM. Details here and student pricing is...
 
Viewing internal signals with ModelSim
Hi all, I am simulating a entity with Modelsim via Xilinx Webpack. Modelsim only displays the input/output signals of the simulated top entity. Is there a way of viewing the internal signals declared...
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problem testing the serial interface code from fpga4fun
I am testing the async_transmission module in xilinx webpack. But I couldn't see the waveform demonstrated in the tutorial for 0x01010101. TxD is always 'x' in my behavioral simulation, what's wrong?...
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Actel SX-A Timing Constraints Issues
Hello all, I helping a colleague debug a timing issue on his SX-A design. I don't have any experience with Actel devices or tools, only Xilinx and Altera, so setting timing constraints with these...
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chip scope
hi i have a question. i have an edk project that i want to debug. so i inserted a chipscope core. my question now is if there is a way to look a signals not in the top level entities. for example i...
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Spartan 3E intefacing for dummies
Hi all, just got Xylo-LM board (Spartan3E + FX2), I was searching for tips and tricks to avoid frying it. In particular, I was interested in interfacing with outside world. So far, I found that...
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Synoplify ???
Aaack, I'm having those awful FPGA Express flashbacks again....
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verilog question, break while loop to avoid combinational feedback during synthesis
Hello, I am puzzled by a statement in a book I am reading: To avoid combinational feedback during synthesis, a while loop must be broken with an @(posedge/negedge clock) statement, such as this while...
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Modelsim XE III 6.x - huge fonts
I'm trying to run the Xilinx version of Modelsim (XE III 6.2g), and it displays everything in HUGE fonts. On my 21" monitor, each char is at least 1" tall. This happens whether I run Modelsim by...
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Is there a means to conditional synthesis in VHDL?
Hi, I am designing a bunch (about 100) of short length tap (5 taps each) FIR. The tap coefficients would be many 1...31. I want to use multiplier adder graph method for the multiplication. That is,...
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timing and timing reports (again)
hi ich have question about timing. i have an edk design with microblaze (using spartan 3e 500) where i use an ip core that i wrote myself. when i implement the design i get the following timing output...
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